Browse Prior Art Database

Performance Issues in VC-Merge Capable ATM LSRs (RFC2682)

IP.com Disclosure Number: IPCOM000003274D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2000-Sep-13
Document File: 9 page(s) / 28K

Publishing Venue

Internet Society Requests For Comment (RFCs)

Related People

I. Widjaja: AUTHOR [+2]

Abstract

VC merging allows many routes to be mapped to the same VC label, thereby providing a scalable mapping method that can support thousands of edge routers. VC merging requires reassembly buffers so that cells belonging to different packets intended for the same destination do not interleave with each other. This document investigates the impact of VC merging on the additional buffer required for the reassembly buffers and other buffers. The main result indicates that VC merging incurs a minimal overhead compared to non-VC merging in terms of additional buffering. Moreover, the overhead decreases as utilization increases, or as the traffic becomes more bursty.

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Network Working Group I. Widjaja

Request For Comments: 2682 Fujitsu Network Communications

Category: Informational A. Elwalid

Bell Labs, Lucent Technologies

September 1999

Performance Issues in VC-Merge Capable ATM LSRs

Status of this Memo

This memo provides information for the Internet community. It does

not specify an Internet standard of any kind. Distribution of this

memo is unlimited.

Copyright Notice

Copyright (C) The Internet Society (1999). All Rights Reserved.

Abstract

VC merging allows many routes to be mapped to the same VC label,

thereby providing a scalable mapping method that can support

thousands of edge routers. VC merging requires reassembly buffers so

that cells belonging to different packets intended for the same

destination do not interleave with each other. This document

investigates the impact of VC merging on the additional buffer

required for the reassembly buffers and other buffers. The main

result indicates that VC merging incurs a minimal overhead compared

to non-VC merging in terms of additional buffering. Moreover, the

overhead decreases as utilization increases, or as the traffic

becomes more bursty.

1.0 Introduction

Recently some radical proposals to overhaul the legacy router

architectures have been presented by several organizations, notably

the Ipsilon's IP switching [1], Cisco's Tag switching [2], Toshiba's

CSR [3], IBM's ARIS [4], and IETF's MPLS [5]. Although the details

of their implementations vary, there is one fundamental concept that

is shared by all these proposals: map the route information to short

fixed-length labels so that next-hop routers can be determined by

direct indexing.

Although any layer 2 switching mechanism can in principle be applied,

the use of ATM switches in the backbone network is believed to be a

very attractive solution since ATM hardware switches have been

extensively studied and are widely available in many different

architectures. In this document, we will assume that layer 2

switching uses ATM technology. In this case, each IP packet may be

segmented to multiple 53-byte cells before being switched.

Traditionally, AAL 5 has been used as the encapsulation method in

data communications since it is simple, efficient, and has a powerful

error detection mechanism. For the ATM switch to forward incoming

cells to the correct outputs, the IP route information needs to be

mapped to ATM labels which are kept in the VPI or/and VCI fields.

The relevant route information that is stored semi-permanently in the

IP routing table contains the tuple (destination, next-hop router).

The route information changes when the network state changes and this

typically occurs slowly, except during transient cases. The word

"des...