Browse Prior Art Database

Implementing the Internet Checksum in Hardware (RFC1936)

IP.com Disclosure Number: IPCOM000004241D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2000-Sep-13
Document File: 16 page(s) / 33K

Publishing Venue

Internet Society Requests For Comment (RFCs)

Related People

J. Touch & B. Parham: AUTHOR

Abstract

This memo presents a techniques for efficiently implementing the Internet Checksum in hardware. It includes PLD code for programming a single, low cost part to perform checksumming at 1.26 Gbps.

This text was extracted from a ASCII document.
This is the abbreviated version, containing approximately 8% of the total text.

Network Working Group J. Touch

Request For Comments: 1936 B. Parham

Category: Informational ISI

April 1996

Implementing the Internet Checksum in Hardware

Status of This Memo

This memo provides information for the Internet community. This memo

does not specify an Internet standard of any kind. Distribution of

this memo is unlimited.

Abstract

This memo presents a techniques for efficiently implementing the

Internet Checksum in hardware. It includes PLD code for programming a

single, low cost part to perform checksumming at 1.26 Gbps.

Introduction

The Internet Checksum is used in various Internet protocols to check

for data corruption in headers (e.g., IP) [4] and packet bodies (e.g,

UDP, TCP) [5][6]. Efficient software implementation of this checksum

has been addressed in previous RFCs [1][2][3][7].

Efficient software implementations of the Internet Checksum algorithm

are often embedded in data copying operations ([1], Section 2). This

copy operation is increasingly being performed by dedicated direct

memory access (DMA) hardware. As a result, DMA hardware designs are

beginning to incorporate dedicated hardware to compute the Internet

Checksum during the data transfer.

This note presents the architecture of an efficient, pipelined

Internet Checksum mechanism, suitable for inclusion in DMA hardware

[8]. This design can be implemented in a relatively inexpensive

programmable logic device (PLD) (1995 cost of $40), and is capable of

supporting 1.26 Gbps transfer rates, at 26 ns per 32-bit word.

Appendix A provides the pseudocode for such a device. This design has

been implemented in the PC-ATOMIC host interface hardware [8]. We

believe this design is of general use to the Internet community.

The remainder of this document is organized as follows:

Review of the Internet Checksum

One's Complement vs. Two's Complement Addition

Interfaces

Summary

Appendix A - PLD source code

A Review of the Internet Checksum

The Internet Checksum is used for detecting corruption in a block of

data [1]. It is initialized to zero, and computed as the complement

of the ones-complement sum of the data, taken in 16-bit units. A

subsequent checksum of the data and checksum together should generate

a zero checksum if no errors are detected.

The checksum allows [1]:

- byte order "independence"

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