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Transfer Device using Self-biased FET Devices

IP.com Disclosure Number: IPCOM000004450D
Publication Date: 2000-Nov-17
Document File: 4 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

Herein is described a Transfer Device using Self-biased FET Devices

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This is the abbreviated version, containing approximately 30% of the total text.

Transfer Device using Self-biased FET Devices

Miniaturization of MOS transistor dimensions has been and continues to be the driving force for improving circuit speed, at lower power, and with improved reliability. Scaling (reducing) the horizontal dimensions of transistors, the oxide thickness of the gates (vertical dimensions), etc. in a manner consistent with the electrical characteristics of CMOS devices is described in reference 1: H.B. Bakoglu "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley Publishing Co. 1990, pages 26-28. Maximizing device drive current when the device is "on" is achieved by using low device threshold voltage (Vth) and short channel lengths. The problem is that the combination of a low Vth voltage and a short channel length results in a high leakage current when the device is in the "off" condition. Device design results in a compromise in which a higher threshold voltage and a longer channel length are used for a lower leakage current, sacrificing device current capability. What is needed is a way to continue to miniaturize CMOS while achieving both high device drive current in the "on" state, and low device leakage current in the "off" state. Disclosed is a technique for applying improved FET devices to transfer device applications.

Prior art Figure 1 shows a conventional FET 100 device as described in reference 1. The value of the substrate voltage is a constant, and is usually measured relative to the source voltage. The drain to source current in the "on" state increases with lower Vth values. Substrate doping, substrate voltage, and channel length L determine Vth. Ids increases with shorter length (Ids ? L-1), so that short channel length is desirable for a higher drive current for a particular FET device. Vth is reduced for short channel lengths L. The "off" leakage current increases with lower Vth such that short channel length devices exhibit high "off" current leakage. The value of Vth and L chosen is a tradeoff between the desire for more drive current in the "on" state, and lower leakage current in the "off" state.

Prior art Figure 2 shows a substrate-control biased FET 200 in which the substrate 205 voltage is modulated by a control circuit 210. Substrate 205 is a well in a SOI (silicon-on-insulator) or conventional FET device structure. The voltage state of select line 215 causes substrate 205 to be connected to Vsub1 220, or to Vsub 2 225, as described in reference 2: USP 5,557,231. Control circuit 210 may cause the substrate 205 voltage to be more positive relative to the source voltage, thus reducing Vth, for a higher Ids "on" current to flow. Conversely, control circuit 210 may cause substrate 205 voltage to be less positive relative to the source voltage, thus increasing Vth for lower Ids "off" current. Modulating the substrate voltage in FET 200 will result in both higher "on" current and lower "off" current fo...