Browse Prior Art Database

Zero Drain Battery Presence Detector

IP.com Disclosure Number: IPCOM000004583D
Original Publication Date: 2001-Feb-23
Included in the Prior Art Database: 2001-Feb-23
Document File: 3 page(s) / 33K

Publishing Venue

Motorola

Related People

Mark K. Taylor: AUTHOR

Abstract

Zero Drain Battery Presence Detector

This text was extracted from a Microsoft Word 97 document.
This is the abbreviated version, containing approximately 100% of the total text.

Zero Drain Battery Presence Detector

Mark K. Taylor

I. Introduction

The absence of the onboard battery on some of Motorola Computer Group x86 architecture mainboard computer products is not easily detectable during the manufacturing process. The battery is installed by hand by prior to the FAT (Final Assembly Test) a step which is sometimes omitted. A missing battery is only detectable during FAT by operator visual inspection, again an error prone process.

The Zero Drain Battery Presence Detector circuit allows the FAT software to detect and report the missing battery. The Zero Drain Battery Presence Detector does not impose a drain current on the battery when the mainboard is not powered. This is important since the battery is expected to be in service for several years and even a small drain current could reduce battery life.

II. Zero Drain Battery Presence Detector Circuit

This circuit is intended for use with a battery that has more than one negative pin that are electrically connected together, for example through the battery case. The mainboard connects one of the negative pins to ground. The mainboard connects one of the remaining pins to a pull-up resistor and to a software readable discrete logic input device on the mainboard. The other side of the pull-up resistor is connected to one of the

power supply voltages.

When the board is powered and the battery is absent the discrete logic input state is pulled up to logic 1 by the pull-up resistor. When the board is powered and the battery is present the discrete logic input state is held at logic 0 by the path to ground through the battery case.

There is no additional drain on the battery since the positive pin is completely isolated from the circuit. Test software running on the mainboard can check the discrete logic input.

0

1