Browse Prior Art Database

USAGE OF DELAY MACRO

IP.com Disclosure Number: IPCOM000004619D
Original Publication Date: 2001-Feb-28
Included in the Prior Art Database: 2001-Feb-28
Document File: 3 page(s) / 25K

Publishing Venue

Motorola

Related People

Bernard Papert: AUTHOR [+3]

Abstract

USAGE OF DELAY MACRO

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USAGE OF DELAY MACRO

Bernard Pappert, Tully Peters, Jason Wang

It is necessary for system on a chip designs to match the rising edge of clocks in different clock domains and sometimes even to the clock at an input or output pad. Matching the rising edge of clocks in different clock domains, that run at different frequencies in normal operation, prevents the smearing of data when transferring data between clock domains, such as during scan test. Different clock domains will have different flip flop loading and therefore the clock trees built by the place and route tool will result in different

delays. The rising edge of the clocks in different domains can be matched by inserting a re-configurable delay macro in front of each clock tree. The 5407 design used the instantiation of 5 delay macros in order to match the clocks in different clock domains to less than 15 ps with just one iteration. The del_6ns shows the initial configuration of a delay macro.

The del_6ns macro is constructed using a family of delay buffers, all have the same footprint and input and output targets so that the cells are interchangeable. The del_6ns macro has a high drive output that is relatively insensitive to output load constructed using inv_4 followed by inv_16, which forms a high drive buffer. The delay buffers actually only vary in poly. The channel length of the devices in the buffers is varied, so that the pair delay (two inversions) varies only 15 ps to 20 ps as the channel length is increased, from one cell to the next, by the minimum granularity allowed by mask prep.

All the delay buffers and inverters used in the delay macro have been verified to be correct, PDRC and LVS clean, and have been timing characterized and added to the standard cell library for use in constructing and timing the delay macro.

The delay macro is built for the first pass in the place and route tool as shown in the del_6ns schematic. A string of unused delay buffers is included for later metal re-configuration. There must be metal blockage over the delay macro in order to allow for later re-configuration during an engineering change order (ECO). Buffer delay cells are interchangeable (poly change) making it possible to change delays. The delay macro should be timed after the first build, which has the correct output loading. The delay macro can be timed because all cell used in its construction having timing files, since they were characterized.

Assume that there are twenty delay buffers, with delays from

100 ps to 580 ps in 20 ps increments, especially 100 ps, 120 ps, 140 ps, ... 580 ps.

Notice that the del_6ns macro has one to fifteen series delay buffers that can be used when the delay macro is re-configured with a metal change. The number of delay buffers included in the delay macro depends upon the delay range to be supported. There are 20 delay buffers. Note that for the del_6ns delay macro there are 15 20**15 4.91 10**20 ways to re-configure the delay macro with only poly and metal ECO thus ...