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IP.com Disclosure Number: IPCOM000004630D
Original Publication Date: 2001-Mar-01
Included in the Prior Art Database: 2001-Mar-01
Document File: 2 page(s) / 26K

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Patrick Clement: AUTHOR



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by Patrick Clement


In receivers for wireless communications there is an increasing need for multi-mode capability. Then, the A-to-D converters embedded in those receivers have to support narrow to medium band signals of the so-called 2G or 2.5G communication standards (GSM, EDGE, CDMA) up to wide band signals of the so-called 3G communication standard (WBCDMA). They might also have to convert signals such as those of the GPS system. Due to the nature of the modulation and encoding used in each of these standards, the resolution needed from the A-to-D converter is not constant.


Considering that the highest resolution is needed for narrow band cases while a lower resolution is acceptable over wide bands, the solution could consist in a converter programmable in such a way that it can exchange resolution against bandwidth.

The highest resolution cases lead to using a sigma-delta converter. The resolution-bandwidth trade-off could be implemented by programming the order of the analog front-end (S? modulator) of such converters. Then, in some of the programmable modes, some circuits would be disabled whenever the maximum order is not needed. This is not the most efficient way of using the silicon area. On the other hand, keeping the order high for every modes does not significantly increase the power consumption in a sigma-delta modulator because the performance of the integrators of the upper degrees is less relevant. The programmability is introduced by optimising the coefficients of a cascaded modulator in a different way for each mode, according to a dedicated sampling frequency.

Accordingly, the following method is used:

The order of the sigma-delta modulator is kept constant.

The order is chosen high enough to provide an appropriate number of noise transfer function (NTF) zeros to be spread across the signal bandwidth.

Preferrably, for 2G, 2.5G, 3G and GPS applications, a 2-2-2 cascaded 6th order modulator is used.

In low resolution mode, non-DC NTF zeros are implemented in second and third stages of the cascaded structure. This allows for supporting a wide bandwidth while keeping the capacitor mismatch issue under control.

In high resolution mode, non-DC NTF zeros are implemented only in the third stage of the cascaded structure. This allows for proper compensation of capacitor mismatch in digital calibration circuits for example.

The coefficients, hence the capacitors of the switched-capacitor network, are optimised for each mode, assuming that the quantisation noise is dominant in high bandwidth/low resolution modes and the thermal noise is dominant in medium bandwidth/high resolution modes.

From one mode to the other, the capacitance level is scaled according to the inverse of their sampling frequency ratio.

The process is iterated by updating the sampling frequency according to the thermal noise degradation resulting from the scaling in order to adequately balance the quanti...