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Device Configuration for Improved Efficiency

IP.com Disclosure Number: IPCOM000004657D
Original Publication Date: 2001-Mar-20
Included in the Prior Art Database: 2001-Mar-20
Document File: 5 page(s) / 58K

Publishing Venue

Motorola

Related People

Bill Goumas: AUTHOR

Abstract

A RF power transistor is configured so that it can be divided up into 2 or more parts. Typically the transistors are made up of a large number of cells (smaller transistors) that are all connected in parallel. This configuration keeps the input side of the device separated into parts that can be biased and or RF driven separately. This allows part of the device to be biased off which results in better efficiency when the transistor is backed off for linear operation.

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Device Configuration for Improved Efficiency

Bill Goumas

Abstract

A RF power transistor is configured so that it can be divided up into 2 or more parts. Typically the transistors are made up of a large number of cells (smaller transistors) that are all connected in parallel. This configuration keeps the input side of the device separated into parts that can be biased and or RF driven separately. This allows part of the device to be biased off which results in better efficiency when the transistor is backed off for linear operation.

Body

Linear Power amplifier stages are backed off from saturation to improve linearity, which results in poor efficiency. This technique allows efficiency to be improved by switching stages off. This technique could also be used with supply modulation to improve the efficiency under backoff conditions. This concept can be applied to very high power devices and amplifiers.

Fig. 1 shows a conventional device configuration and the proposed new configuration for a conventional "6 cell" 10W device. This technique could be applied to any size or type of device.

The drain or output side of the transistor is tied together, but the new device is divided up into 2 or more parts on the gate or input side. For this example the transistor is shown divided into 3 parts.

Fig. 3 shows a schematic of how this device would be set up in a RF power amplifier circuit. The input is split into 3 parts that have separate bias connections labeled Vbias, Vturn1 and Vturn2. These voltages (Vturn1 and Vturn2) are switched on and off to turn part of the device off to improve the efficiency. Vturn1 and Vturn2 can also be swept together to supply modulate the amplifier with minimal current.

Fig. 2 shows the simulated results for IM and efficiency versus output power as the circuit is changed from the complete device on to turning off 1/3 and 2/3 of the device. Efficiency is improved at the backed off level of ~2W average for this device. IM characteristics show that with 2/3 device on, the drive-up is very similar to the complete device and with 1/3 device on the IM is ~-25dBc at rated power. The output matching network has been optimized for best performance compromise over the 3 different biasing conditions.

This technique results in efficiency that is improved over conventional amplifier circuits. Switching bias to part of a device is much easier and simpler than switching in and out various loading conditions. An amplifier could be supply modulated with minimal current requirements by varying the voltage on the gate. Because of high input impedance of Field Effect Transistors, current required is on the order of milliamps. This is unlike traditional supply modulation of the drain or collector voltage. This concept would allow simplified "supply modulation" to be done with an amplifier built with 1 or more paralleled output stages in a multi-stage amplifier. Fig. 4 shows a block diagram of this concept.

Fig. 1 CONVENTIONAL 10WATT 6-CELL DEVICE

NEW DEVICE CON...