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A novel word-line driver for a five transistor SRAM

IP.com Disclosure Number: IPCOM000004659D
Original Publication Date: 2001-Mar-20
Included in the Prior Art Database: 2001-Mar-20
Document File: 4 page(s) / 53K

Publishing Venue

Motorola

Related People

Paul Bonwick: AUTHOR

Abstract

A novel word-line driver for a five transistor SRAM

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 34% of the total text.

A novel word-line driver for a five transistor SRAM

by Paul Bonwick

Background : SRAM requirements for a programmable logic device

The SRAM cells used for configuration storage within a programmable logic device (e.g. an FPGA) typically have different requirements to SRAM cells used for data storage.

Programmable logic devices typically need great flexibility with connectivity between the various programmable logic blocks. For this reason routing resources within programmable logic devices are typically at a premium. It is therefore a great advantage for the configuration storage SRAM cells to use the minimum of routing resources.

The configuration stored within the SRAM cells of a programmable logic device is typically written infrequently (usually only at power-up), and only read as part of a memory test operation. Therefore the speed of read/write operations is of little consequence during normal operation. The principle disadvantage of slow operation would be tester time (not discussed here).

Background : 6T SRAM 4T SRAM)

A 'normal' six transistor SRAM is shown below.

This contains a latch consisting of two back-to-back inverters. The latch is used top store the data within the SRAM. Typically the inverters will have a strong ntype pull-down transistor and a weak ptype pull-up transistor. Each side of the latch is connected via a read/write transistor (A B) to a bit line (bit and bit-bar). The two transistors (A B) are controlled by one word line.

In a read operation bit lines are both pre-charged high before the word-line is activated. When the word-line is activated one bit line is pulled low by the strong pull-down transistor. A sense amp detects which bit line is pulled low and the SRAM is read.

In a write operation one bit line is driven low before the word-line is activated. When the word-line is activated this low will overpower the weak pull-up within the SRAM and flip the cell.

The description of a four transistor SRAM is typically identical to this except that resistors replace the weak ptype pull-up transistors.

The Problem

The five transistor SRAM is shown below.

The advantage this has over the six transistor is that only one bit line and one read/write transistor is used. Having just one bit line halves the number of vertical tracks used for configuration, thus freeing them to be used as routing resources within the programmable logic device. The loss of one read/write transistor will also reduce the area of the SRAM cell.

The read/write transistor connects the latch to the one bit line controlled by the word-line. The inverter 'X' needs to be weak so that it can be overpowered by the charge on the bit line in order to write the SRAM. I.e. both the ntype pull-down transistor and the ptype pull-up transistor need to be weak. The strength of the inverter 'Y' is less important, it should be small to reduc...