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MULTI-CHANNEL MOSFETs for HIGH VOLTAGE RESISTANCE

IP.com Disclosure Number: IPCOM000004660D
Publication Date: 2001-Mar-20
Document File: 7 page(s) / 137K

Publishing Venue

The IP.com Prior Art Database

Abstract

To realize high breakdown voltage and low channel resistance (also known as low "on" resistance) for a high voltage MOSFET power device a new structure and process have been devised. This new structure enables the creation of a four terminal MOSFET by using multiple p-channel and n-channel MOSFETs that share the same drain and source terminals, yet maintain separate gate terminals. The structure utilizes the basic mechanism of channel depletion caused by the both side reverse biased p-n junction diode.

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MULTI-CHANNEL MOSFETs for HIGH VOLTAGE RESISTANCE

To realize high breakdown voltage and low channel resistance (also known as low "on" resistance) for a high voltage MOSFET power device a new structure and process have been devised. This new structure enables the creation of a four terminal MOSFET by using multiple p-channel and n-channel MOSFETs that share the same drain and source terminals, yet maintain separate gate terminals. The structure utilizes the basic mechanism of channel depletion caused by the both side reverse biased p-n junction diode. This structure is shown in the following drawings as being based upon an epi substrate, but it could also be realized in other standard substrates such as those used in BCD or other MOS type technologies.

STRUCTURE

The first set of figures are a top view and two cross sectional views of a single unit cell in the proposed device. Each of the cells have a p-channel and an n-channel transistor. The P+ and the N+ region of the left side area contacted by a metal layer and thus form the transistor source . The right side P+ and N+ region form the transistor drain. The device as depicted can conduct current by use of two carriers, hole and electron, in a separate channel.

The next figure (3-1) is a schematic representation of multi-channel depletion diode structure created using this proposed single unit cell.. The figures a, b, c, d depict the depletion region of the above multi channel depletion mode diode structure (3-1) under 4 different bias conditions to help explain the novelty of the invention-

a) Depletion region when a low reverse bias voltage is applied

b) Depletion region creating multi channel diode cells combined with many cells

c) Depletion region when a middle reverse bias voltage is applied to the multi channel diode cells

d) Showing full depletion when a high reverse bias voltage is applied.

The next figure (Fig. 5) shows two of these units as shown above combined. One should note that both P- layer and N- layer are depleted as the P-N layer consisting of a P- layer and a N- layer are reverse biased in the normal use of this cell unit. Also observe that the P- layer is located between the N- layers.

Both sides of the P- layer begin to deplete from their borders with the N- layer (Fig.6). The N- layer also depletes from the borders of the P- layer as the N- layer also exists between the P- layers.

The next figure (Fig. 7) shows complete channel depletion.

Thus, this device can reduce channel resistance because of the enabled two channels per unit cell. This novel configuration is what provides the advantage of both high breakdown voltage and low channel on resistance.

It can be seen that a device would likely consist of many of these cells (Fig.8).

PROCESS

A fabrication process for the above structure may be comprised of the following steps:

1) Prepare a P- substrate

2) N- implant photo and N- implant for the drift layer of the n-channel transistor

3) N implant photo resist removal and N-drift layer anneal