Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

OPTIONAL EEPROM DATA INVERSION CODED INTO THE EEPROM ITSELF

IP.com Disclosure Number: IPCOM000004662D
Original Publication Date: 2001-Mar-21
Included in the Prior Art Database: 2001-Mar-21
Document File: 2 page(s) / 6K

Publishing Venue

Motorola

Related People

Eric Boulian: AUTHOR

Abstract

OPTIONAL EEPROM DATA INVERSION CODED INTO THE EEPROM ITSELF

This text was extracted from a RTF document.
This is the abbreviated version, containing approximately 84% of the total text.

OPTIONAL EEPROM DATA INVERSION CODED INTO THE EEPROM ITSELF

by Eric Boulian

INTRODUCTION

Traditionally, the highest Vt state of an EEPROM cell is considered to be the erased state. Depending on the supplier, the family of product or the customer, this erased state may be preferred to be read as a "0" or as a "1 ". Both cases coexist in the market.

It is therefore an object of the design to render optional the erased state of the memory by the mean of a control bit, placed itself into the memory array.

PROBLEMS TO BE SOLVED

1. EEPROM Wipe out state should be independent from the wipe out techniques.

2. New products to be backward compatibles with all kinds of older non-volatile memory products.

3. Prepares compatibility with next generation of non-volatile memory products.

4. Compatibility with all competitors nonvolatile memory products.

PROPOSED SOLUTION

The basic principle of the design is to use one bit of the shadow bytes to define the data logic value of the EEPROM program or erase state.

1(set) EEPROM array erased state reads as $FF.

0(clear) EEPROM array erased state reads as $00.

The principle of the shadow bytes consists in storing in a non-volatile way, some customer options. This is done by reading the shadow bytes EEPROM cells, during RESET and to transfer there contains some latches, at the end of RESET. The stable values of these latches is then used in order to configure the chip according to the EEPROM stored options.

Let's now call EEFF the concerned EEPROM bit and SEEFF its copy in the EEPROM register.

The default erase state of a data byte is $FF. When EEFF bit in the EEPROM array is programmed to zero, SEEFF is cleared after reset and the data path from the MCU to the EEPROM array and the reverse path from the EEPROM array to the MCU include an inverter, such that the erase state of a data byte reads as $00. Please note the data path from the EEPROM array to the shadow control registers (including this one) is not inverted.

Then, after the final test, or after execution of an instruction like bulk erase, all EEPROM cells Vt's are set to high. A RESET execution will then force the default value into SEEFF, which considers a high Vt as "1". A "1" is then transferred to SEEFF at the end or RESET and the EEPROM is considered to be erased at "1".

Let's now suppose that the EEFF bit is programmed to "0" as the SEEFF value is still "1". If a RESET occurs, SEEFF is turned to "0" at the end of this RESET and the erased state is now considered to be a "0".

Note that EEFF is always read by the CPI as a "1" as if programmed to 0, it inverts its own value when read by the CPU.

Of course it is necessary that no data inversion occurs during RESET execution, so that the real EEFF value can be loaded to SEEFF bit. If required (SEEFF 0) the data path inversion will be placed after the SE...