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USING AN INSERTED INTERPOSER BETWEEN DYNAMIC RANDOM ACCESS MEMORY (DRAM) TO MONITOR A BUS

IP.com Disclosure Number: IPCOM000004684D
Publication Date: 2001-Apr-05
Document File: 4 page(s) / 12K

Publishing Venue

The IP.com Prior Art Database

Abstract

Computer systems commonly use busses to transfer data between devices that include processors, storage devices and input/output (I/O) devices. Many of such busses use one or more data lines, which are electrical conductors on which signals are used to transfer data in concert with a clock signal and/or one or more control signals. Binary busses make use of signals that transition between a high and a low voltage level, indicating a binary one or zero value for purposes of transferring information. In the case of binary busses, only one device connected thereto is able to transmit data at any given time.

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This is the abbreviated version, containing approximately 44% of the total text.

USING AN INSERTED INTERPOSER BETWEEN

DYNAMIC RANDOM ACCESS MEMORY (DRAM) TO MONITOR A BUS

Computer systems commonly use busses to transfer data between devices that include processors, storage devices and input/output (I/O) devices. Many of such busses use one or more data lines, which are electrical conductors on which signals are used to transfer data in concert with a clock signal and/or one or more control signals. Binary busses make use of signals that transition between a high and a low voltage level, indicating a binary one or zero value for purposes of transferring information. In the case of binary busses, only one device connected thereto is able to transmit data at any given time.

Presently, ternary busses are used that use signals that transition among three voltage levels including a high, a low and an intermediate voltage level. Two devices connected to a ternary bus are able to transmit data to each other, substantially simultaneously, with each device employing various methods to derive the data being transmitted by the other device. By allowing both devices to substantially simultaneously transmit data, the ternary bus nearly doubles the rate at which data is transmitted. A high or low level on a ternary bus indicates that both devices are transmitting a high or low signal, respectively. An intermediate level indicates that one device is transmitting a high signal while the other is transmitting a low signal. However, determining which device is transmitting the high signal and which is transmitting the low signal is not possible to discern from an intermediate level signal, itself. Each device must use the data it is transmitting to derive the data being received, and debugging such a bus to diagnose problems or confirm functionality is rendered more difficult. Diagnostic tools, such as a logic analyzer, fail to monitor data being transferred on a ternary bus between two devices by the simple attachment of probes to the bus conductors. A logic analyzer or scope cannot typically discern between signals being sent and signals being received, and also cannot discern between voltage levels having small differences as in the case of ternary busses, thereby preventing signal reconstruction.

Additionally, an increasing number of busses now transfer data at rates high enough that the attachment of probes to conductors of a bus will add discontinuities (such as impedance) to the bus and alter the electrical properties of the bus such that data integrity is adversely effected or the functionality of the bus is impaired. Further, as computer systems move towards the use of sophisticated multi-stage pipelines and large symmetric multiprocessor (SMP) shared cache structures, the ability to debug, analyze, and verify actual hardware becomes increasingly difficult, during development, testing, and normal operations. Monitoring complex events, to capture useful debug and performance information, must be fast and not alter events.

An inserted interpo...