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Method to Facilitate Double Half-Duplex Transfers on a SPI Bus

IP.com Disclosure Number: IPCOM000004694D
Original Publication Date: 2001-Apr-11
Included in the Prior Art Database: 2001-Apr-11
Document File: 3 page(s) / 39K

Publishing Venue

Motorola

Related People

Brian W. Pruss: AUTHOR

Abstract

Method to Facilitate Double Half-Duplex Transfers on a SPI Bus

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This is the abbreviated version, containing approximately 65% of the total text.

Problem

Existing SPI Bus configurations allow for half-duplex or full-duplex data transfers between a Master and single Slave only. This is theoretically unnecessary, as the communication lines for Master-to-Slave and Slave-to-Master transfers are physically separated.

Solution

The method described in this paper can allow the Master to communicate with two slaves at once, receiving from one and sending to the other in a double half-duplex transfer. This should improve bus performance by reducing time spent by SPI members waiting for the bus to become free.

The Bus Multiplexer forms the heart of a double half-duplex capable SPI interface. This is a block of logic controlled by the Master SPI member, which controls all SPI lines going to Slaves. An example diagram of its use in a SPI interface is illustrated in Figure 1.

The Bus Multiplexer contains three registers, each of which must have at least as many bits as there are to be Slaves on the interface. How the registers are accessed is specific to each implementation, but the simplest manner is to memory-map them and allow them to reside on the processor's memory bus. The Incoming Request register indicates all Slaves currently requesting permission to send a message to the Master and is a bitmap of all Slave Request lines. The Slave Request Grant register is used by the Master to select which Slave currently has permission to send data. Only one bit of the Slave Request Grant register is to be set at any given time. Outgoing Select is map of all Slaves to which the Master wishes to end messages.

If a Slave's Slave Request Grant bit is set, but its Outgoing Select bit is not, the MOSI line to that Slave is a masked-to-NULL version of the Master's MOSI line. Similarly, if a Slave's Outgoing Select bit is set, but its Slave Request Grant bit is not, the MISO line from that Slave is ignored.

Any message protocol used with this bus must provide knowledge of message lengths. In a double half-duplex message session, the Master must clock out enough bytes to fully receive the incoming Slave's message. (Number of bytes Max( length of Master-to-Slave message, length of Slave-to-Master message ).) Any Null bytes received outside of a message by any SPI member must be considered as padding for another member's message and therefore ignored.

Examples of all five data transfer types are given below.

Message Sequences

Single Half Duplex Message, Master to Slave

Master sets bit corresponding to desired target slave in Outgoing Select register of Bus Multiplexer.

Master then asserts Slave Select and starts clocking out data. Bus Multiplexer will clock out Nulls to Master.

Full Duplex Message, Master to Single Slave

Master sets bit corresponding to desired target slave in Outgoing Select and Slave Request Grant registers of Bus Multiplexer.

Master then asserts Slave Select and starts clocking out data to Slave, while receiving data from slave.

Single Half Duplex Message, Slave to Master

Slave(s) wishing to send data assert their ...