Browse Prior Art Database

N-well resistivity reduction by N-well accumulation capacitor

IP.com Disclosure Number: IPCOM000004701D
Publication Date: 2001-Apr-12
Document File: 6 page(s) / 131K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for N-well resistivity reduction by N-well accumulation capacitor. Benefits include reduced GTL driver size, reduced capacitive loading, and increased speed.

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 53% of the total text.

N-well resistivity reduction by N-well accumulation capacitor

Disclosed is a method for N-well resistivity reduction by N-well accumulation capacitor. Benefits include reduced GTL driver size, reduced capacitive loading, and increased speed.

The N-well resistivity of advanced technologies (.25µ and .18µ) is increasing when compared to older technologies due to lower doping density and use of shallow-trench isolation techniques (see Table 1 in Figure 1). Although the linear dimensions are smaller, the net resulting GTL driver size is increased because of the vertical path in the current flow due to STI. For GTL drivers which require ~10O impedance, the N-well penalty is large, roughly doubling the NMOS size. Therefore, to keep area and capacitance in check, the N-well resistivity must be reduced. One method is to place a gate on the N-well which does not require a shallow trench for N+ to N+ isolation, lowering the resistivity and variations. This concept is extended to modulating the gate which helps lower the N-well resistivity further, and also avoids the capacitance penalty (see Figure 2).

The increased N-well resistivity increases the GTL driver size. This scheme has a potential to reduce the GTL driver size by ~23%-32% or more. The reduced driver reduces capacitive loading, helping speed up bus transitions and speed. The reduced area represents opportunity to reduce die area or add on chip bypass capacitor.

Conventionally, N-well ballasting has been used to protect the NMOS device. For ballasting action, an N-well is placed in series with a NMOS device resulting in reduced drive strength of the driver.

In MOS accumulation mode, the amount of charge available for conduction provides a good measure of resistivity. For example, a capacitor, Q CV, where C (gate) for .18µ ~10.8 fF/µm2 and the minimum voltage V across the capacitor is obtained at the GTL driver pad voltage (Vo1, is 0.5V for GTL+ bus and 0.2V for the new 1V GTL bus) [1.3-0.5] 0.8V or 1.1V, resulting in a Q 8.64 or 11.88 fC/µm2 54,000 or 74,250 e/µm2.

For an N-well 2.67x 1017/cm3 (or 2x 1013/cm2 implant) and a well 0.75 µm deep, the number of carriers are:

Qn (2x1013 )x (1x10-4) x (1x10-4) 200,000 e/µm2.

The gate-modulated N-well can, therefore, contribute ~27% 37% of the available charge resulting in lowered N-well resistivity (see Figure 3).

If the N-well also has the threshold adjustment dose, then these also contribute to the available charge. If the threshold adjustment adds to the N-well dose (such as Phosphorous deep implant, followed by Arsenic threshold implant µm23x1012/cm2 or 30,000/µm2), then the total available charge in the N-well is 230,000/µm2. Therefore, the capacitive contribution is ~23-32%.

One major contributor to the N-well resistance is the low-doped vertical section where the current travels before reaching the higher-doped lower section of the well. This secti...