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SLEW RATE CONTROL CIRCUITS FOR MEMORY

IP.com Disclosure Number: IPCOM000004727D
Publication Date: 2001-Apr-23
Document File: 8 page(s) / 404K

Publishing Venue

The IP.com Prior Art Database

Abstract

The circuits described here relate generally to drivers of a solid state memory device and in particular to a circuit for controlling slew rates in such drivers.

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 16% of the total text.

SLEW RATE CONTROL CIRCUITS FOR MEMORY

The circuits described here relate generally to drivers of a solid state memory device and in particular to a circuit for controlling slew rates in such drivers.

Integrated circuits can be provided to communicate data over a communication bus. The term "data" here refers to address, control, and/or the actual content of a memory location. The integrated circuits include both a data transmitter, or driver circuit, and a receiver circuit. Communicating data signals on the communication bus can be complicated and is the subject of extensive studies relating to transmission lines. To reduce data signal ringing and signal interference, the rise time or slew rate of a signal transmitted on the data bus is often controlled. In addition, an impedance mismatch between the integrated circuit driver and the communication bus can increase the signal ringing and interference. As such, it is common to employ techniques to reduce impedance mismatch.

In addition to controlling data communication slew rate and driver circuit impedance matching, a reduction in the communication bus lines is desired. That is, two data lines can be provided between integrated circuits. One data line communicates in a first direction, while the second data line is used for data communication in an opposite second direction. It is desired to reduce the two data lines by using a single data communication line. By using a single data line which communicates data in two directions simultaneously, signal interference between the two data signals creates additional difficulties in reliable data communication. As such, reference circuitry can be used to subtract a data signal, which is being transmitted, from the data signal received to isolate the received data.

For the reasons stated above, and for other reasons stated below, there is a need for a bidirectional data communication circuit which can provide slew rate control on transmitted data and maintain adequate noise margin on received data signals of a memory device.

A data communication circuit includes a delay line circuit coupled to receive an output data signal. The delay line circuit includes a number of output connections for providing the output data signal, where a signal provided on each of the output connections is delayed from a previous one of the output connections. A data driver circuit is provided with a number of stage circuits coupled to the output connections of the delay line circuit such that a slew rate of a data signal transmitted by the data driver circuit can be controlled by the delay line circuit. A data receiver circuit is coupled to the delay line circuit. A slew rate of a reference voltage signal coupled to the data receiver circuit can be controlled by the delay line circuit such that the slew rate of the data signal transmitted by the data driver circuit and the slew rate of a reference voltage sig...