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Automatic flow to track and solve NAC errors and DFD items

IP.com Disclosure Number: IPCOM000004732D
Publication Date: 2001-Apr-23
Document File: 1 page(s) / 7K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of workflow to track and solve NAC (electro-static discharge diode) errors and design for debug (DFD) items. Benefits include improved turnaround and productivity.

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Automatic flow to track and solve NAC errors and DFD items

Disclosed is a method of workflow to track and solve NAC (electro-static discharge diode) errors and design for debug (DFD) items. Benefits include improved turnaround and productivity.

The workflow begins with the CAD runset using base CAD software which finds NAC errors (see Figure 1). The locally-developed run set analyzes all the errors specified by the reference table, and the correct solution is identified. The prepare command file places preset design cells or polygons with a specialized placement scheme and routing algorithm, according to the existing design. An internal loop checks the results until a maximum number of errors are addressed.

This automated error detection and correction replaces the manual procedure that may take between 1-5 days per each layout functional block. This solution improves mask designer productivity and reduces layout insertion and verification time. It also implements DFD (Design For Debug) items in an opportunistic way.

Fig. 1

Disclosed anonymously