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A sense amplifier design to enhance the testability of differential dynamic logic circuits

IP.com Disclosure Number: IPCOM000004792D
Publication Date: 2001-May-29
Document File: 5 page(s) / 85K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a sense amplifier design to enhance the testability of differential dynamic logic circuits. Benefits include enhanced testability of differential logic circuits, which results in enhanced system reliability.

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A sense amplifier design to enhance the testability of differential dynamic logic circuits

Disclosed is a sense amplifier design to enhance the testability of differential dynamic logic circuits. Benefits include enhanced testability of differential logic circuits, which results in enhanced system reliability.

The disclosed Testability Enhanced Sense Amplifier (TESA) has two modes of operation, Normal and Test. In Normal mode, the amplifier performs the standard function of restoring differential signals in high speed, small signal, and dynamic logic circuits. In Test mode, the amplifier improves the response predictability of defective circuits in the presence of degraded differential signals, reducing the outgoing DPM and increasing the reliability of shipped parts.

Designers of sense amplifiers used in low voltage swing (LVS) dynamic logic circuits assume sufficient difference between the complementary signals at the input of the sense amplifier. If the differential signal falls below this threshold, the output of the sense amplifier is unpredictable and impacts the testability of the circuits.

Many defects cause differential signals to degrade in a way that the voltage difference between complementary signals falls below the threshold assumed by designers. Defects such as resistive and full opens, bridges and shorts among two or more signal nodes, as well as bridges between a signal line and either VDD or Ground are examples of such defects. Some of these defects, like resistive and full opens are expected to increase with copper processes.

The conventional sense amplifier provides unpredictable results when sensing degraded differential signals. Some defective circuits may pass as good parts. Passing the test-process is no guarantee that the part is not defective. A circuit could fail during field operation and cause poor system reliability.

The disclosed design addresses the problem of unpredictable results from defective LVS circuits. Many defects cause differential signals to degrade so that their voltage difference falls below the specified value assumed by designers.

Conventional techniques to detect defects fall into two categories, multiple defect detection and voltage and temperature stress. For multiple defect detection, the conventional practice consists of using a large number of test vectors that excite and propagate defective signals in different ways. These vectors are obtained by current ATPG tools by assuming multiple fault models for each defect or by SAT n-detection, requiring that each SAT fault is detected at least n times when the test set is applied.

For voltage and temperature stress during test application, another approach consists of testing under stress such as high/low voltage testing, high/low temperature testing, or a combination of both. These techniques are effective with CMOS circuits not using differential logic. In this ...