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Method to use the IOAPIC to deliver SMI messages to processors

IP.com Disclosure Number: IPCOM000004795D
Publication Date: 2001-May-30
Document File: 2 page(s) / 90K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use the IOAPIC to deliver SMI messages to processors. Benefits include a complete IOAPIC-based BIOS solution for SMI and other message delivery that can be extended to include the removal of the discreet SMI signal from the processor and chipset.

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 100% of the total text.

Method to use the IOAPIC to deliver SMI messages to processors

Disclosed is a method to use the IOAPIC to deliver SMI messages to processors. Benefits include a complete IOAPIC-based BIOS solution for SMI and other message delivery that can be extended to include the removal of the discreet SMI signal from the processor and chipset.

Conventionally, the SMI signal is delivered to all CPUs in a system by a discrete signal from the chipset to the CPU. The disclosed method enables the delivery of the SMI signal through the IOAPIC messaging mechanism instead of a discrete SMI signal (see Figure 1). The IOAPIC-based SMI delivery mechanism can be extended so that a specific CPU can be targeted for priority reception by programming the IOAPIC pin redirection table of the SMI signal (see Figure 2).

For a non-ACPI environment, the MP table (see Figure 3) is used to report to an OS that a particular IOAPIC Input signal is being used for SMI. This IOAPIC pin has to be dedicated for SMI delivery hence cannot be used for other purposes of regular interrupt delivery.

For an ACPI environment, the Interrupt source override structure of the MAPIC ACPI table is used to report to the OS the SMI signal routing through the IOAPIC (see Figure 4). The SMI signal mapping entering the IOAPIC input pin should be reported as reserved.

IOAPIC can be integrated or external

Fig. 1

Interrupt Source Override Structure

Field

Byte Length

Byte Offset

Description

Type

1

0

2 Interrupt Source Override

Length

1

1

10

Bus

1

2

0 Constant (ISA)

Source

1

3

Bus-Relative Interrupt Source (IRQ)

Global System Interrupt Vector

4

4

The Global System Interrupt Vector that this Bus-Relative Interrupt Source Triggers

Flags

2

8

MPS INTI Flags

Fig. 2

MPS INTI Flags

Local APIC Flags

Bit Length

Bit Offset

Description

Polarity

2

0

Polarity of the APIC I/O Input Signals

00 Conforms to the Bus Specifications

(For example, EISA is Active-Low for Level-Triggered Interrupts)

01 Active High

10 Reserved

11 Active Low

Trigger Mode

2

2

Trigger Mode of the APIC I/O Input Signals

00 Conforms to the Bus Specifications

(For example, ISA is Edge Triggered)

01 Edge Triggered

10 Reserved

11 Level Triggered

Reserved

12

4

Must be 0

Fig. 3

SMI Entry in the ACPI Tables

Type 2

Length 10

Bus 0 (ISA)

Source 017h (An example where INTIN_PIN_23 is being used for SMI)

Global System Interrupt Vector 017h (An example where INTIN_PIN_23 is being used for SMI)

Flags 0Ah (Reserved signal)

Fig. 4

Disclosed anonymously