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Method to use the IOAPIC to deliver NMI messages to processors

IP.com Disclosure Number: IPCOM000004796D
Publication Date: 2001-May-30
Document File: 2 page(s) / 90K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use the IOAPIC to deliver NMI messages to processors. Benefits include a complete IOAPIC-based BIOS solution for NMI and other message delivery that can be extended to include the removal of the discreet NMI signal from the processor and chipset.

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Method to use the IOAPIC to deliver NMI messages to processors

Disclosed is a method to use the IOAPIC to deliver NMI messages to processors. Benefits include a complete IOAPIC-based BIOS solution for NMI and other message delivery that can be extended to include the removal of the discreet NMI signal from the processor and chipset.

Conventionally, the NMI signal is delivered to all CPUs in a system by a discrete signal from the chipset to the CPU. The disclosed method enables the delivery of the NMI signal through the IOAPIC messaging mechanism instead of a discrete NMI signal (see Figure 1). The IOAPIC-based NMI delivery mechanism can be extended so that a specific CPU can be targeted for priority reception by programming the IOAPIC pin redirection table of the NMI signal (see Figure 2).

For a non-ACPI environment, the MP table (see Figure 3) is used to report to an OS that a particular IOAPIC Input signal is being used for SMI. This IOAPIC pin cannot be used for other purposes of interrupt delivery.

For an ACPI environment, the Interrupt source override structure of the MAPIC ACPI table is used to report to the OS the SMI signal routing through the IOAPIC (see Figure 4).

The existing ACPI table structure enables a platform designer to stipulate which IOAPIC sources should be enabled as non-maskable. Any source that is non-maskable is not available for use by other devices.

IOAPIC can be integrated or

Fig. 1

Non-maskable Source Structure

Field

Byte Length

Byte Offset

Description

Type

1

0

3 Non-maskable Interrupt Source

Length

1

1

8

Flags

2

2

Same as MPS INTI Flags

Global System Interrupt Vector

4

4

The Global System Interrupt Vector that this NMI Triggers

Fig. 2

MPS INTI Flags

Local APIC Flags

Bit Length

Bit Offset

Description

Polarity

2

0

Polarity of the APIC I/O Input Signals:

00 Conforms to the Bus Specifications

(For example, EISA is Active-Low for Level-Triggered Interrupts)

01 Active High

10 Reserved

11 Active Low

Trigger Mode

2

2

Trigger Mode of the APIC I/O Input Signals

00 Conforms to the Bus Specifications

(For example, ISA is Edge Triggered)

01 Edge Triggered

10 Reserved

11 Level Triggered

Reserved

12

4

Must be 0

Fig. 3

NMI Entry in the ACPI Tables

Type 2

Length 10

Bus 0 (ISA)

Source 016h (An example where INTIN_PIN_22 is being used for NMI)

Global System Interrupt Vector 016h (An example where INTIN_PIN_22 is being used for NMI)

Flags 05h (Active High Edge trigerred signal)

Fig. 4

Disclosed anonymously