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Dynamic detection of RDRAM devices in the absence of SPD data

IP.com Disclosure Number: IPCOM000004797D
Publication Date: 2001-May-30
Document File: 2 page(s) / 16K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of dynamic detection of RDRAM devices in the absence of SPD data. Benefits include elimination of the use of an EEPROM to store SPD data.

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Dynamic detection of RDRAM devices in the absence of SPD data

Disclosed is a method of dynamic detection of RDRAM devices in the absence of SPD data. Benefits include elimination of the use of an EEPROM to store SPD data.

The disclosed method enables the system BIOS to dynamically detect and size RDRAM devices on a RDRAM Inline Memory Module (RIMM), Small Outline RDRAM Inline Memory Module (SORIMM) or Graphics Performance Module (GPM). The requirement for an EEPROM to store SPD data is eliminated.

Conventionally, SPD on the RIMM, SORIMM and GPM is used to detect the amount of RDRAM memory in a system. The SPD data is stored on an EEPROM located on each memory module.

Initialization of the channel must follow a strict sequence of events to achieve successful operation of the RDRAM devices on the channel. The following steps outline the general steps that must be taken for proper channel initialization, detection and sizing.

1. System reset restarts the chipset and state machines and prepares them for initialization.

2. System BIOS performs the main memory initialization.

3. Setup the direct clock generator (if required).

4. Perform the chipset RAC initialization.

5. Initiate SIO reset on the channel.

6. Initialize the RDRAM test 77h register to 000h.

7. Initialize the chipset configuration registers to the defaults required during initialization.

8. Execute Broadcast Register Write IOP to RDRAM register test 78h,

data =04h.

9. Execute Broadcast Register Write IOP to RDRAM register test 34h,

data =040h.

10. Reset all RDRAM devices by sending Set Reset IOP.

11. Delay 10┬Ás.

12. Execute a Clear Reset IOP to all RDRAM devices, which are now in Power Down mode.

13. Execute Broadcast Register Write IOP to RDRAM register test 34h,

data =00h.

14. Execute Broadcast Register Write IOP to RDRAM register test 78h,

data =00h.

15. Assign unique serial device IDs to each RDRAM device on the channel.

16. Program the number of RDRAM devices on the channel into the chipset registers or save it for the future programming of the chipset registers.

17. Program all timing parameters in the chipset registers based on data read from the SPD EPROMs on the each memory module.

18. Bring all RDRAM devices out of Power Down mode.

19. Send the Fast Clock Initialization IOP to all RDRAM devices to prepare them to operate at the selected frequency.

20. Initialize RDRAM cores; perform current calibration, temperature calibration, and precharge/refresh all banks of all RDRAM devices.

21. Perform channel levelization.

22. Program power down configuration options: self-refresh and low power self-refresh.

23. Set the Initialization Complete Bit in chipset registers to start normal maintenance operations.

Autodetection of the number of RDRAM devices present on a memory module

During step #15, when the System BIOS assigns unique serial device IDs to each RDRAM device on the channel, a read to the same register is performed after the Serial ID is written. If this read is successful then the temporary count for the numbe...