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Array devices attachment

IP.com Disclosure Number: IPCOM000004808D
Publication Date: 2001-Jun-11
Document File: 4 page(s) / 131K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of attaching array devices as ball grid array (BGA) or chip scale package (CSP) to a PC board during the assembly process. Benefits include prolonged component life.

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Array devices attachment

Disclosed is a method of attaching array devices as ball grid array (BGA) or chip scale package (CSP) to a PC board during the assembly process. Benefits include prolonged component life.

The disclosed method connects a number of BGA balls to create one solid connection. The solid connection could be divided and have a solder mask between the pads. This arrangement prolongs the component's life through temperature cycles due to an increase in the area that resists shear stress. The larger area enables the use of components with small standoff, ceramic components, and wafer-level components on an FR4 board material.

A trend in conventional processor packaging solutions is smaller packages to reduce costs. Increasing usage of CSP means the chip size is similar to the packages. With WLP, solder balls are attached at wafer level. Reliability is a challenge for these small packages, which generally have reduced stand-off height and no compliant lead. The CTE mismatch between the substrate and the package is causing excessive stress on the small joints and failure during temperature cycling. When a silicon die with CTE of 2.5 ppm/deg is placed on a FR-4 substrate with 18-25 ppm/deg, in case of WLP or flip chip, underfill is usually required. The underfill process fills the package with compliance material, which reduces the joint stress caused by expansion of the substrate. Figure 1 illustrates a conventional 7x7 array of pads used with a CSP device. The device has identical balls placed on the pad pattern.

The disclosed method requires the circuit board design to leave large pads in some locations under the package (see Figure 2), especially at the corners farthest from the natural point the highest stress area. The designer can use power, ground or signal pads as long as they can be tied together. It could take 2, 3, 4 or more. During the assembly of the boards, solder paste is printed on the large pads. The array device is then placed on the pads. After the solder reflow process, the tied balls form a large bond to the substrate. By increasing the solder at the tied up area, the joints absorb more stress during thermal cycling and extend the fatigue life.

Figure 3 illustrates a 7x7 array of pads with increased pad size. In example A, the four corners have larger pads combining the 4 original pads into one. The sample device is placed on a Land pattern. In example B, the large pads are separated by a solder mask. In example C, the four corners are 2 large pads combining 2 original pads into one separated by solder mask. The same CSP device is place on a Land pattern. In example D, the four corners have 2 large pads combining 2 original pads into one.

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Disclosed anonymously