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METHOD AND APPARATUS TO PROGRAM VARIABLE DELAYS IN TIMING CRITICAL CIRCUITS

IP.com Disclosure Number: IPCOM000004835D
Publication Date: 2001-Jul-03
Document File: 2 page(s) / 32K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and apparatus to program variable delays in timing critical circuits. Benefits include ease of use, flexibility, and reversibility.

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METHOD AND APPARATUS TO PROGRAM VARIABLE DELAYS IN TIMING CRITICAL CIRCUITS

Disclosed is a method and apparatus to program variable delays in timing critical circuits. Benefits include ease of use, flexibility, and reversibility.

The disclosed solution addresses the challenge of analyzing and fixing critical speed paths during microprocessor silicon debug. The apparatus provides variable timing delays to match the actual silicon performance to the required silicon performance.

The actual performance of the complex circuits in silicon cannot be always predicted accurately by conventional simulation techniques. Changing the circuit behavior in silicon is required to optimize the performance/functionality of the circuit. Conventional solutions include the following methods:

Focused ion beam

Selective metal mask tape out

Power supply control

Pico-probing

The focused ion beam solution (see Figure 1) is costly, time consuming, and extremely risky. The parts are mostly non-functional after this irreversible procedure. It renders the circuit unusable for further timing control.

The selective metal mask tape out solution is time consuming, costly, and irreversible.

The power supply control solution purports to provide delay in the circuits by varying the power supply. However, the entire chip is affected and cannot be used for localized speed path debug.

The pico-probing solution involves introducing delays in the circuit manually using a mechanical probe to alter the parasitics along the signal line. This procedure is also very risky in that it is destructive to the part, and time consuming.

The disclosed solution provides ease of use through software programming enabled at the chip interface. The timing delay is flexible and can be varied in either direction. The technique is non-destructive to the part and also reversible. The cost of implementing this feature is minimal because of the use of software programming.

The disclosed implementation utilizes a read/write register to store option mode bits to control the delay elements along the option-mode path (A to B in Figure 2). The circuit implementation consists of having multiple paths which each contain different delay elements. Each of the variable delay paths ends in a select element (MUX in Figure 1) before converging into the option-mode node (B in Figure 2). The select element specifies that a particular delay path is connected to the option-mode node. The control for the select element is provided by the option mode bits in the programmable register. It is easily interfaced via the chip-level pins for software programming.

Fig. 1

Fig. 2

Disclosed anonymously