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Design for Ultra-Low Skew-Matched Frequency Divider Clock Circuit

IP.com Disclosure Number: IPCOM000004843D
Publication Date: 2001-Jul-10
Document File: 2 page(s) / 17K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a design for an ultra-low skew-matched frequency divider circuit for high-speed clock distributions. The design uses a divide-by-1 complementary metal-oxide semiconductor (CMOS) circuit that delay-matches a divide-by-2 CMOS for clocking applications. In previous designs, the divide-by-2 and the divide-by-1 circuits showed a finite delay mismatch (typically between 10 and 20 ps) that sums linearly with each cascaded stage. The disclosed design provides much more accurate delay matching. This allows a significant reduction of clock skew on the chip, both between different frequency domains and within the same domain if used in the phase locked loop (PLL) feedback path.

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Design for Ultra-Low Skew-Matched Frequency Divider Clock Circuit

Disclosed is a design for an ultra-low skew-matched frequency divider circuit for high-speed clock distributions. The design uses a divide-by-1 complementary metal-oxide semiconductor (CMOS) circuit that delay-matches a divide-by-2 CMOS for clocking applications. In previous designs, the divide-by-2 and the divide-by-1 circuits showed a finite delay mismatch (typically between 10 and 20 ps) that sums linearly with each cascaded stage. The disclosed design provides much more accurate delay matching. This allows a significant reduction of clock skew on the chip, both between different frequency domains and within the same domain if used in the phase locked loop (PLL) feedback path.

If a chip requires multiple clock domains distributed from the same PLL, divider circuitry is added after the PLL. In order to keep the insertion delays between the clock domains as close as possible to reduce skew, matching circuits have to be introduced in some of the path. The same approach can match the feedback path of the PLL to the path between clock input pin and PLL, in case the on-chip frequency differs from the external clock input to the chip.

The disclosed design is based on a divide-by-2 circuit that utilizes a D flip flop with a negative feedback path. In the divide-by-1 circuit, only the second latch of the flip flop is active and its input is controlled by two pass gates: one triggered by the positive edge of the clock, the other by the negative edge. The inputs of the pass gates are tied to positive and negative supply voltage (VCC and VSS) to enable toggling of the divide-by-1 output with every clock edge. Both circuits (divide-by-1 and divide-by-2) contain additional inverters for exact delay matching.

The schematic of both circuits is shown in FIGs. 1 and 2.

Simulations of the circuit show a zero ps delay mismatch between the divide-by-2 and the divide-by-1 output. This statement is based on the following assumptions:

1. Both the divide-by-2 and the divide-by-1 circuits are in close proximity such that there is no process, voltage or temperature difference between the two.

2. Careful layout work to match routing and sizing orientation of transistors in critical paths.

The disclosed design would benefit high-speed CMOS designers and manufacturers.

Figure 1: Divide by 1

Figure 2: Divide by 2

Disclosed Anonymously.