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Circuit to Improve I/O Buffer Speed

IP.com Disclosure Number: IPCOM000004844D
Publication Date: 2001-Jul-10
Document File: 3 page(s) / 97K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an impedance control bit translator circuit that improves input/output (I/O) buffer timings. It amplifies the swing of the process, voltage and temperature (PVT) compensated predriver stage of the I/O buffer, thus maximizing the benefits obtainable from the PVT bits. In effect, this circuit speeds up the I/O buffers, improving microprocessor performance.

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 72% of the total text.

Circuit to Improve I/O Buffer Speed

Disclosed is an impedance control bit translator circuit that improves input/output (I/O) buffer timings. It amplifies the swing of the process, voltage and temperature (PVT) compensated predriver stage of the I/O buffer, thus maximizing the benefits obtainable from the PVT bits. In effect, this circuit speeds up the I/O buffers, improving microprocessor performance.

Improving core speed alone does not suffice to improve the performance of a microprocessor. The current bottleneck is the I/O buffer speed, which needs to be enhanced to exploit the fullest benefit of the core speed.

Some current microprocessors use an I/O buffer that has a process, voltage and temperature (PVT) compensated predriver stage. Depending on the PVT conditions, the strength of the predriver will adjust itself to meet the buffer timings. The strength of the predriver stage typically is controlled with five bits that are generated by the impedance control units. However, the swing of the PVT strength ranges from 8 in the FFFF corner to only 16 in the slow corner. A wider swing, from 1 to 31, for instance, would be beneficial.

In current microprocessors, the impedance control unit compares the buffer impedance against a standard calibrated external resistance (50 ohm 1%) to generate five bit compensation bits to track the PVT of the core. To shrink the tco window on both sides, the most appropriate bit combination would ensure the widest spread of the bit combinations across the FFFF and RSSS corner. The wider the spread, the better the control or tracking of the PVT.

In current microprocessors, the sensitivity of the PVT bits across the PVT conditions is not great. This is so due to the presence of the electrostatic discharge control (ESD) resistors in series with the n-channel metal-oxide semiconductor (NMOS) legs, which significantly affects buffer impedance. The poor sensitivity to the PVT conditions prevents the I/O buffer timings from exploiting the maximum benefits out of the impedance control circuits.

Techniques exist to improve the bit combinations in the slower corner by passing them through a fixed offset of an adder circuit. Unfortunately, using this technique, the buffer timings can be improved either only on the fast corner or on the slow corner, but never both. For example, the bits are improved by fixed offset by passing them through an adder, resulting in better buffer timing at the slow corner (tcomax). However, the buffer timing at the fast corner (tcomin) is impacted negatively by making it too fast to make the hold equation buffer. Any identical attempt to improve the tcomin will in turn deteriorate the tcomax of the buffer.

The disclosed translator circuit amplifies the swing of the PVT compensated predriver stage of the I/O buffer, as shown in FIG. 1. The circuit consists of some combination gates, with inputs and outputs five bits wid...