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EQUALIZATION CIRCUITS FOR MEMORY

IP.com Disclosure Number: IPCOM000004906D
Publication Date: 2001-Jul-11
Document File: 4 page(s) / 75K

Publishing Venue

The IP.com Prior Art Database

Abstract

The techniques described below are directed to the use of equalization circuits to help increase signal-to-noise ratio (SNR) in integrated circuit (IC) environments such as solid state memory, e.g. dynamic random access memory (DRAM), static RAM, and non-volatile memory such as flash memory.

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EQUALIZATION CIRCUITS FOR MEMORY

The techniques described below are directed to the use of equalization circuits to help increase signal-to-noise ratio (SNR) in integrated circuit (IC) environments such as solid state memory, e.g. dynamic random access memory (DRAM), static RAM, and non-volatile memory such as flash memory.

Processor clock speeds in IC environments are continuing to increase and show no signs of reaching a plateau. As a result, the bit rates in the rest of the IC environment are also being forced to rise to maintain an optimum performance level in the overall electronic system. However, as bit rates increase, communication channels, such as those between IC dies and between modules a in a DRAM subsystem, suffer from lower SNR at high frequencies.

In high speed communications, the information signal, for instance the content, address, or control signal in a memory subsystem, has a wide spectral range. DRAM communication channels exhibit a frequency-dependent loss characteristic that can distort a signal on the channel. Accordingly, an equalization scheme may be used to compensate for the loss in a given spectral range, by applying an inverse channel characteristic to the signal.

Fig. 1 illustrates a block diagram of part of an IC subsystem 104 enhanced with an equalization block 106. The IC subsystem has a communication channel 110 between two logic devices 108 and 112. The channel 110 may be a single conductor line of a parallel or point to point bus. A driver 114 and a receiver 118 are coupled to the channel 110. The equalization block 106 in this version is an analog high-pass filter applied at the driver 114. The frequency response of the filter may be designed to essentially cancel the effects of frequency-dependent loss in the channel 110, to improve the SNR in the driven signal.

Fig. 2 shows a block diagram of another application of the equalization scheme, in a memory subsystem 204. This subsystem 204 has a multi-drop bus as the DRAM I/O channel 210 to which each logic device of the subsystem 204, namely the memory controller 208 and one or more DRAM devices or modules 212, are connected. Here, the equalization blocks have digital signal processing (DSP) capabilities that operate upon digitized versions of the driven or received signals at each logic device of the subsystem 204, namely the memory controller 208 and one or more DRAM devices or modules 212. As an alternative to such a purely digital implementation, the selected equalization scheme could be implemented by a combination of analog techniques (Fig. 1) and digital schemes, depending upon the effects observed and the permitted manufacturing cost of the subsystem. Examples of equalization functions that may be adapted for use in a memory subsystem include those used in personal computer (PC) modems.

The physical structures, be it hardwired logic or perhaps a programmable controller, that pe...