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IMPEDANCE CONTROL CIRCUIT IN MEMORY

IP.com Disclosure Number: IPCOM000004907D
Publication Date: 2001-Jul-11

Publishing Venue

The IP.com Prior Art Database

Abstract

Circuitry to interface between components of a digital solid state memory sub-system are well-known. However, increasing signal speeds, such as on the order of 500 megabit transfers per second, have made these interface circuits increasingly complex. For example, due to increasing signal speeds, it may be desirable to match impedances between components of the memory sub-system, such as between a transmitting amplifier in a memory controller and a controlled impedance signal coupling in the memory device, to reduce the amount of signal reflection that may occur.

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 12% of the total text.

IMPEDANCE CONTROL CIRCUIT IN MEMORY

Circuitry to interface between components of a digital solid state memory sub-system are well-known. However, increasing signal speeds, such as on the order of 500 megabit transfers per second, have made these interface circuits increasingly complex. For example, due to increasing signal speeds, it may be desirable to match impedances between components of the memory sub-system, such as between a transmitting amplifier in a memory controller and a controlled impedance signal coupling in the memory device, to reduce the amount of signal reflection that may occur.

Impedance control circuits, such as described above, are well-known. However, it would be desirable to have an economic on-chip implementation of a feedback control circuit in which the circuit impedance being adjusted or controlled may be updated even while digital signal samples are being transmitted via the interface circuitry.

Referring now to the figures:

Figure 1 is a schematic diagram illustrating two alternative methods of termination;

Figure 2 is a block diagram illustrating an impedance control circuit;

Figure 3 is a circuit diagram illustrating the output buffer of Figure 2 in greater detail;

Figure 4 is a block diagram illustrating a portion of the circuit of Figure 2 in greater detail;

Figure 5 is a block diagram illustrating a portion of the circuit of Figure 2 in greater detail;

Figure 6 is a block diagram illustrating a portion of the circuit of Figure 2 in greater detail;

Figure 7 is a plot showing the current vs. voltage (I/V) characteristic of a typical metal-oxide semiconductor (MOS) transistor;

Figure 8 is a circuit diagram illustrating a portion of the circuit of Figure 3 in greater detail.

As silicon processing technology advances, the speed of logic components made from silicon continues to increase. As a result, it is desirable to have high speed interface circuitry to transfer electrical signals, such as digital solid state memory signals, into and out of integrated circuit memory chips capable of operating at these increased speeds. To transmit high speed electrical signals with interface circuitry, it is desirable that a properly terminated, controlled impedance circuit be employed. Termination circuits or structures to accomplish this may be implemented either on-chip or off-chip; however, typically, on-chip termination techniques provide cost and speed advantages over off-chip termination techniques.

Figure 1 is a schematic diagram illustrating both source and parallel termination approaches. Either approach may be employed in the interface circuitry described here; however, the version described hereinafter is implemented as a source termination circuit to capture cost and speed advantages that may be available with that approach. As illustrated in Figure 1, in both approaches, electrical signals, such as d...