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CHANNEL FILTERS FOR MEMORY

IP.com Disclosure Number: IPCOM000004908D
Publication Date: 2001-Jul-11
Document File: 5 page(s) / 33K

Publishing Venue

The IP.com Prior Art Database

Abstract

The technique described below are directed to the use of channel filters to increase signal-to-noise ratio (SNR) in a solid state memory environment, be it dynamic random access memory (DRAM), static RAM, or non-volatile memory such as flash memory.

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CHANNEL FILTERS FOR MEMORY

The technique described below are directed to the use of channel filters to increase signal-to-noise ratio (SNR) in a solid state memory environment, be it dynamic random access memory (DRAM), static RAM, or non-volatile memory such as flash memory.

Referring to Fig. 1, a conventional memory subsystem 100 having a controller 104 is shown in block diagram form. The subsystem 100 has conventional solid state memory input/output (I/O) circuits that act as an interface between a shared, multi-drop, parallel bus 112 and the memory core in a number of memory IC dies or modules 108. Such I/O circuits have a receiver 114 that generates, from the incoming bus signal, a received signal that is suitable for input to logic gates built using a particular fabrication process, such as complimentary metal oxide semiconductor (CMOS). The receiver 114 is followed by a latch 116 whose output feeds a memory core 120 which includes the storage array and row/column decoder circuitry (not shown). In the drive path, a latch 124 is fed with output data that is latched and then driven by a driver 128 into, in this case, the same bus conductor or line that was used for the received signal. Note that there is no filtering involved in the I/O channel of such a subsystem, either in the receive path or the drive path.

A problem with the conventional approach described above is that as the bit rate is increased to keep up with increasingly faster processors, the SNR may deteriorate, thus limiting the ability to increase the bit rate.

Accordingly, what is proposed here is a technique that uses filtering to compensate for non-ideal channel characteristics, and particularly those characteristics which reduce the SNR at high bit rates. Fig. 2 depicts a block diagram of a memory IC die or module 208 which features three different types of channel filtering. First, a filter block 206 may be placed between the receiver-driver 210 and a conductor 212 of the bus 112, to act on the bus signals directly. This is referred to as bus side filtering. As an alternative or in addition to bus side filtering, a filter may be incorporated into the receiver-driver 210 circuitry. Finally, filtering may also be performed by filter block 226 positioned before the latches 116, 124, on the so-called chip or module side of the subsystem.

The filtering on the bus side (filter block 206) would preferably be continuous time analog filtering, whereas the chip side filtering (filter block 226) would feature discrete time digital filtering given the digital nature of the information received from the memory core and the availability of logic circuitry to implement digital filtering on the chip side. Such logic circuitry could be designed to implement inverse-channel transform digital signal processing (DSP) filters. The filtering that would be incorporated into the receiver circuitry could support a type of integration or over-sampling function. The selected filtering implementation could...