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A concept for an all digital multi phase clock generation by frequency controlled delay lines

IP.com Disclosure Number: IPCOM000004910D
Publication Date: 2001-Jul-11
Document File: 3 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a concept for an all-digital multi-phase clock generation by frequency controlled delay lines. Benefits include robustness, portability, simplicity, and correct operation under a wide range of frequency.

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A concept for an all-digital multi-phase clock generation by frequency controlled delay lines

Disclosed is a concept for an all-digital multi-phase clock generation by frequency controlled delay lines. Benefits include robustness, portability, simplicity, and correct operation under a wide range of frequency.

Advanced microprocessors utilize several phases of the system clock for synchronization and communication of different units. Providing, and distributing these important, and global signals across the relatively long distances on chip is a challenging task. Local clock generators are required to provide various units with clock signals aligned or with a fixed relationship to the original system clock. The disclosed concept introduces a new all-digital concept for local multi-phase clock generation.

Conventionally, PLLs are the most widely used solution for generating accurate clock signals with variable frequency within a relatively wide range. However, large noise-levels in digital VLSI circuits increase the design-complexity of the PLLs. Thus PLLs are unlikely to be employed as local clock generators, which might be frequently needed in a single chip. DLLs have also been proposed as multi-phase clock generators. However robustness, accuracy, and the frequency scope of DLLs are also open issues subject to current research.

Fig. 1 shows a high-level block diagram of the proposed clock generator. The goal is to match the total delay of the delay element, which here (as an example) includes six variable delay segments with 60° phase difference. The binary signal M controls the delay of the delay elements, such that the total delay of the delay element TD=Tclk (min)* (M*A+1).

The value A<

An integrated ring oscillator is designed to generate a fixed frequency proportional to the minimum delay time of the delay line, which is equal to the period time of the maximum allowable incoming clock frequency, Clk. The relation between the frequency of the ring oscillator and the minimum delay of the delay line is fixed and supply-voltage independent.

Later the output of the ring oscillator is divided through a set of flip-flops such that a periodic signal Clk2 with a frequency fclk2 fclk (min)/N is provided. The value N>>1 is a relatively large fixed integer and has an important impact on the accuracy of the clock generation. As N increases, the accuracy of the calculation of the binary control signal for the delay element increases. This low frequency signal is utilized as both set and reset signal for an adder, which is set then increments for each period of the incoming clock, clk.

After a full period time of the Clk2 clock, the output of the adder is K= N*Tclk(min) Tclk. Assuming ...