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More Stable Flip-Flop with Self-biased Circuit Feedback for sub-0.75V Operation

IP.com Disclosure Number: IPCOM000005034D
Publication Date: 2001-Aug-01
Document File: 4 page(s) / 148K

Publishing Venue

The IP.com Prior Art Database

Abstract

Miniaturization of MOS transistor dimensions has been and continues to be the driving force for improving circuit speed, at lower power, and with improved reliability. Scaling (reducing) the horizontal dimensions of transistors, the oxide thickness of the gates (vertical dimensions), etc. in a manner consistent with the electrical characteristics of CMOS devices is described in reference 1: H.B. Bakoglu "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley Publishing Co. 1990, pages 26-28.

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More Stable Flip-Flop using Self-biased FET Devices

Miniaturization of MOS transistor dimensions has been and continues to be the driving force for improving circuit speed, at lower power, and with improved reliability. Scaling (reducing) the horizontal dimensions of transistors, the oxide thickness of the gates (vertical dimensions), etc. in a manner consistent with the electrical characteristics of CMOS devices is described in reference 1: H.B. Bakoglu "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley Publishing Co. 1990, pages 26-28. Maximizing device drive current when the device is "on" is achieved by using low device threshold voltage (Vth) and short channel lengths. The problem is that the combination of a low Vth voltage and a short channel length results in a high leakage current when the device is in the "off" condition. Device design results in a compromise in which a higher threshold voltage and a longer channel length are used for a lower leakage current, sacrificing device current capability. Flip-flop circuits using these devices are less stable because they are more easily triggered by on chip noise, or by an event such as an alpha particle collision. What is needed is a way to continue to miniaturize CMOS while achieving both high device drive current in the "on" state, and low device leakage current in the "off" state for increased flip-flop stability. Disclosed is a more stable flip-flop circuit in which self-biased FET devices are used to control the substrate well voltage bias of both the NMOS and PMOS type of flip-flop devices. As a result, flip-flop stability is enhanced even as voltages are scaled to lower values (voltages of 1 volt or less, for example).

Figure 1 shows a well-known prior art static RAM (SRAM) storage cell consisting of flip-flop 105, select transistors 210 and 240, and a word line (WL) and bit lines (BL and BL/n) for selection. The state (node 145 high or low, and node 185 low or high) of the flip-flop is set by the voltage momentarily applied to nodes 145 and 185 in the conventional manner during write. The state of the flip-flop is sampled during read. The p-doped substrate well associated with the NMOS devices is connected to the lowest power supply (ground as shown in Figure 1). The n-doped substrate well associated with the PMOS devices is connected to the highest power supply (V as shown in Figure 1). NMOS and PMOS devices are indicated by well-known conventional symbols. The substrate well bias is not adjustable in the conventional flip-flop circuit. Figure 2 shows a modified flip-flop in which the NMOS and PMOS devices have been replaced by self-biased NMOS and PMOS devices, and the corresponding substrate well connections removed. Self-biased FET devices are described in reference 2: USP 5,998,847. The gate of each self-biased device is coupled to its own substrate well using a resistor, such that the gate voltage modulates th...