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Method for leakage compensation for low swing, high speed caches, register files, and buses

IP.com Disclosure Number: IPCOM000005065D
Publication Date: 2001-Aug-07
Document File: 2 page(s) / 24K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for leakage compensation for low swing, high speed caches, register files, and buses. Benefits include reduced voltage swing, improved read after write latency, and reduced sense amp latch latency.

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Method for leakage compensation for low swing, high speed caches, register files, and buses

Disclosed is a method for leakage compensation for low swing, high speed caches, register files, and buses. Benefits include reduced voltage swing, improved read after write latency, and reduced sense amp latch latency.

The disclosed method includes a design for an apparatus for caches and register files (see Figure 1), and buses (see Figure 2). The method utilizes NMOS (instead of PMOS) for precharge nodes on the bit line or bus to reduce voltage swing by VT. A leakage-compensation NMOS is used for each precharge NMOS. The voltage of the precharged node is kept slightly below VCC-VT by ratioing the gate widths of the leakage NMOS.

Benefits include reduced voltage swing for low power reduction, improved read after write latency, and reduced sense amp latch latency due to better common mode voltage.

Fig. 1

Fig. 2

Disclosed anonymously