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Method for scan testing domino circuits

IP.com Disclosure Number: IPCOM000005122D
Publication Date: 2001-Aug-15
Document File: 2 page(s) / 27K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for scan testing domino circuits. Benefits include the capability to determine fault coverage loss in domino circuits.

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Method for scan testing domino circuits

Disclosed is a method for scan testing domino circuits. Benefits include the capability to determine fault coverage loss in domino circuits.

Background

Domino logic is sometimes called dynamic logic or precharge logic. It is a design technique used for ultra-high speed circuit applications where conventional static CMOS design cannot achieve the timing goals.

Scan design is a testing methodology in which logic is added to internal system state to make it directly observable and controllable from the pins of the chip. Scan is conventionally thought to be inapplicable to domino circuits. When scan is used to modify the system state, it is critical that no other internal circuitry prevents the state from changing. At any given time, domino circuits are either being actively pulled High (by a precharge clock) or actively pulled Low (by an evaluate clock or by data), leaving no time window during which scan can modify the system state.

Because no conventional method for scanning of domino logic exists, functional tests are relied on to determine fault coverage or its loss is accepted as inevitable.

Description

The disclosed method enables scan testing to be applied to domino circuits. The two components of this invention which enable domino scan are: the set-dominant latch scan cell and the clock gating logic. The set-dominant latch uses a full keeper rather than the precharge clock. As a result, the latch retains its data while the upstream domino circuits are precharged, enabling it to be an observation point for scan. For example, one gate-level implementation of the scan logic is shown in Figure 1. The clock gating logic forces the set-dominant latch's data inputs to logical 1 and the clock input to logical 0 (see Figure 2). The set-dominant latch's output is determined exclusively by the full keeper and enables the latch to be a control point for scan. (Note that the disclosed method include the logical behavior of the clock gating logic; many logically equivalent gate-level implementations are possible.)

Fig. 1

Fig. 2

Disclosed anonymously