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Switched memory I/O architecture for multi-channel video capture and home cable broadcast

IP.com Disclosure Number: IPCOM000005129D
Publication Date: 2001-Aug-15

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an architecture for switched memory I/O for multi-channel video capture and home cable broadcast. Benefits include the capability to swap large data blocks of data in and out main memory by switching memory banks rather than using conventional bus transactions. Additional benefits include scalable multi-channel video capture up to 16 channels, enhanced manipulation of video streams for improved, smart video environments, and support for studio multi-track audio recording scalable to 36 channels.

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Switched memory I/O architecture for multi-channel video capture and home cable broadcast

Disclosed is an architecture for switched memory I/O for multi-channel video capture and home cable broadcast. Benefits include the capability to swap large data blocks of data in and out main memory by switching memory banks rather than using conventional bus transactions. Additional benefits include scalable multi-channel video capture up to 16 channels, enhanced manipulation of video streams for improved, smart video environments, and support for studio multi-track audio recording scalable to 36 channels.

The transfer of large blocks of data is supported by an extended-size memory card that integrates two banks of memory, a switch, and an interface to an I/O stream. The switch is used to connect one bank of memory to the main memory bus for access by the host. The switch connects the other bank to the I/O interface. While the data in one bank is being accessed by the CPU, the other bank is being filled.

Detailed Description

A block diagram of the architecture is contained in Figure 1. Three different switched memory modules are illustrated. One module captures broadcast content from a cable source. One module captures video from a set of cameras placed around a space. One module distributes video via cable to a set of TVs distributed around the space. This system example is suitable for supporting a smart environment. The design includes input and output both being accomplished with the same architecture.

A schematic of electrical bus switch positions is contained in Figure 2. The graphic shows only a single set of connections for clarity. Each bus consists of approximately 100 wires. The two portions of the graphic represent the two basic access configurations. One configuration uses CMOS 24-bit bus exchange switches. Logical bus switching may also work. The bus switch contains a set of four switches per signal. Only 2 of the 16 possible configurations of these 4 switches are used in switched memory I/O.

A specific instance of the switched memory I/O architecture is contained in Figure 3. The illustrated instance is designed to capture four analog video channels of analog video into a platform with PC100 SDRAM memory. On the left side of the figure, a pair of 32-MB memory banks is each connected to the bus switch. A bus switch is also connected to the DIMM memory bus of the host and to an FPGA that routes pixels to the switch. The switch connects the FPGA to one memory bank and connects the PC100 bus to the other bank.

The board has a microcontroller that is represented at the bottom of Figure 3. The microcontroller provides the control interface with the host PC via a serial port. The use of memory-mapped I/O to control the board reduces the latency of bus swaps. The serial port simplifies the design and make an interrupt available for use. The microcontroller also initial...