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Delay Locked Loop Optimization for CDMA Receivers

IP.com Disclosure Number: IPCOM000005372D
Original Publication Date: 2001-Sep-13
Included in the Prior Art Database: 2001-Sep-13
Document File: 7 page(s) / 151K

Publishing Venue

Motorola

Related People

Chris Smart: AUTHOR

Abstract

This DLL optimization ensures that the effective loop bandwidth is automatically adjusted in the presence of interference to reduce jitter while maintaining the ability to rapidly track the received signal

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Delay Locked Loop Optimization for CDMA Receivers

by Chris Smart

Abstract

This DLL optimization ensures that the effective loop bandwidth is automatically adjusted in the presence of interference to reduce jitter while maintaining the ability to rapidly track the received signal.

Introduction

A delay locked loop (DLL) is typically used within a direct sequence spread spectrum receiver to maintain alignment between the received pseudo-noise code sequence and a locally generated replica. Poor alignment results in the degradation of the error rate performance of the receiver at best or complete loss of the signal at worst.

The bandwidth of the DLL determines the rate at which the loop can track the received signal and its jitter performance in the presence of interference. The selection of the bandwidth normally involves a trade-off between tracking speed and susceptibility to interference; that is, a wide bandwidth allows for rapid tracking but at the expense of increased jitter, while a narrow bandwidth minimises the jitter but at the expense of a reduced tracking rate.

This paper presents an optimization to the generation of the error signal in a direct sequence spread spectrum receiver DLL such that a high tracking rate can be maintained without suffering the penalty of increased loop jitter in the presence of interference.

Description of DLL

The DLL in a direct sequence spread spectrum receiver uses a timing error detector (TED) to derive an estimate of the misalignment between the received PN sequence and a locally generated despreading reference. This error signal is then used to control the sampling instants at the input of the receiver, allowing it to track the input signal.

A traditional design for the TED in a first order DLL is shown in Figure 1. The received signal S(t) is despread (1 and 2) with two PN code sequences, offset in chips by some fixed amount, termed the 'early' and 'late' PN references. The resulting despread signals are integrated (3 and 4) over some period and the energy of each (Ee(t) and El(t)) is calculated (5 and 6). The error signal, E(t), is calculated (7) as the difference between the early and late energies scaled by a factor k :

[1]

The value of k determines the bandwidth of the DLL: large k allows a rapid loop tracking rate but at the expense of increased loop jitter; small k reduces loop jitter but at the expense of a slow tracking rate. Finally the timing adjustment signal, A(t), is calculated by accumulating (8) the error signal.

The traditional DLL can be improved by modifying the way in which the error signal is calculated, such that the value of loop gain, k, can be chosen without having to make the compromise between loop tracking rate and loop jitter.

This modification comprises a normalization of the error signal, such that :

[2]

Figure 2 shows this modification with the normalization applied by the division at 9.

The effect of normalizing the error signal is that the value k' can be used to control the tracking rate o...