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Method for cost optimizing capacitor selection for voltage regulation applications

IP.com Disclosure Number: IPCOM000005406D
Publication Date: 2001-Sep-27
Document File: 4 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for cost optimizing capacitor selection for voltage regulation (VReg) applications. Benefits include improved cost savings with a direct relationship to technical performance, and the improved capability to make detailed technical design selection of VReg solutions, improved capability to develop controlled equivalent series resistance (ESR) components.

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Method for cost optimizing capacitor selection for voltage regulation applications

Disclosed is a method for cost optimizing capacitor selection for voltage regulation (VReg) applications. Benefits include improved cost savings with a direct relationship to technical performance, and the improved capability to make detailed technical design selection of VReg solutions, improved capability to develop controlled equivalent series resistance (ESR) components.

Terms

Di/dt: Change in processor current per unit time

VCPU: Nominal operating voltage for the processor,

Vdroop : Voltage droop, the amount of voltage drop from nominal processor voltage

VReg: Motherboard voltage regulation

Background

With increasing di/dt and decreasing processor voltage, capacitor cost per motherboard has skyrocketed in the last few years. In 1996, motherboard capacitors cost approximately $4.50 to support a processor VReg circuit. In 2001, motherboard capacitors cost approximately $15-$20 to support a processor VReg circuit.

Design Engineers typically use previous VReg circuits as a basis for next generation designs. These next-generation designs are often include a large quantity of the same capacitor to simplify equivalent series resistance (ESR) estimations. The designs are often modified iteratively in the lab to reduce cost, eliminating the possibility of considering all possible capacitor combinations. Determining the cost savings that would result from a relaxation of the Vdroop specification is not possible with the conventional methodology.

Description

The disclosed method provides a new, lower-cost baseline from which DEs can begin their circuit-level analysis for each next-generation design. Further, by detailing the Vdroop percentage of each solution, cost savings opportunities may be identified that would result from any relaxation in the Vdroop specification.

This method is unique in that it considers the physical layout of the capacitors, providing an accurate model for temperature and physical constraints, as well as allowing printed circuit board impedance to be considered on a per-location basis. This model provides DEs with a reduced-cost baseline, saving time in the development of next-generation VReg circuits and reducing the material cost of the final circuit. Suppliers are able to develop controlled ESR components that specifically meet the needs of the processor di/dt to further reduce circuit cost. In addition, the cost can be associated with the tightening or relaxation of the Vdroop specification.

The key elements of the method consist of user inputs, computation, and outputs.

User inputs include:

Temperature constraints by location

Geometry constraints, including height constraints under the processor as well as height constraints under the processor heatsink

Di/dt curve, in time-divided stages; this curve is generated from simulation and/or testing of the processor or SPICE model to simulate di/dt behavior

Impedance per foot of the power plane in the printed circ...