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DELAYED CODED SQUELCH CIRCUITRY FOR USE WITH RADIO RECEIVERS

IP.com Disclosure Number: IPCOM000005416D
Original Publication Date: 1980-Aug-01
Included in the Prior Art Database: 2001-Oct-10
Document File: 2 page(s) / 90K

Publishing Venue

Motorola

Related People

Kent P. Kebernik: AUTHOR

Abstract

The main purpose of the delayed coded squelch circuitry is to unsquelch a radio receiver immediately upon detection of the proper RF carrier, and squelch the radio receiver again if the proper squelch code has not been detected after a predetermined period of time. This time period may be equal to the time it takes the normal coded squelch decoder in the receiver to detect a correct squelch code.

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MOTOROLA Technical Disclosure Bulletin Vol. 1 No. 1 August 1980

DELAYED CODED SQUELCH CIRCUITRY FOR USE WITH RADIO RECEIVERS By Kent P. Kebernik

  The main purpose of the delayed coded squelch circuitry is to unsquelch a radio receiver immediately upon detection of the proper RF carrier, and squelch the radio receiver again if the proper squelch code has not been detected after a predetermined period of time. This time period may be equal to the time it takes the normal coded squelch decoder in the receiver to detect a correct squelch code.

   Referring to Flgure 1, when the proper RF carrier is detected by a radio receiver, the carrier indicate signal is a logic high, which is applied to one input of AND gate 101 and to a differentiating circuit 102. The differentiating circuit 102 is responsive to the high going transistor of the carrier indicate signal for providing a trigger pulse to a monostable 103. When triggered, the monostable 103 provides a logic high for a predetermined time. The monostable output provides a timing window that is sufficiently long to allow a normal receiver squelch decoder to detect the proper coded squelch if it is present. The logic high from the monostable 103 is applied to one input of an OR gate 104, and the OR gate 104 applies a logic high to the other input of AND gate 101. When both inputs of the AND gate 101 are high, its output goes high and unsquelches the receiver. In order for the output of the AND gate 101 to remain high after the monostable output goes low, a logic high must be applied to the other input of the OR gate by the PL in- dicate signal from the coded squelch decoder. If, for example, an incorrect code has come in, the PL in- dicate signal from the coded squelch decoder will remain at a logic low. Consequently, after the monostable 103 times out, AND gate 101 will go low and again squelch the radio receiver.

  The time that the radio receiver is falsely unsquelched is limited to the...