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N-CYCLE N-BIT SUCCESSIVE APPROXIMATION A/D

IP.com Disclosure Number: IPCOM000005436D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2001-Oct-10
Document File: 2 page(s) / 82K

Publishing Venue

Motorola

Related People

Thomas L. Hopkins: AUTHOR

Abstract

The circuit shown in Figure 1 is designed to do an e-bit successiva approximation analog.to-digital conversion In 8 clock cycles. This improves the number of conversions per second of the circuit Over most commercial S/A A/D devices which require 9 clock cycles to complete the same conversion. The same technique may be used to construct any S/A A/D converter with N bits of resolution. In this case the conversion will require N clock cycles rather than N + 1 clock cycles as required by the widely used cow figuration.

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Technical Developments Volume 2 January 1982

N-CYCLE N-BIT SUCCESSIVE APPROXIMATION A/D

By Thomas L. Hopkins

   The circuit shown in Figure 1 is designed to do an e-bit successiva approximation analog.to-digital conversion In 8 clock cycles. This improves the number of conversions per second of the circuit Over most commercial S/A A/D devices which require 9 clock cycles to complete the same conversion. The same technique may be used to construct any S/A A/D converter with N bits of resolution. In this case the conversion will require N clock cycles rather than N + 1 clock cycles as required by the widely used cow figuration.

   The timing diagram, shown in Figure 2, illustrates the operation of the circuit. During the first 7 clock cycles the circuit operates in the same manner as a normal successive approximation register, such as the MC14549. The difference is primarily in the 8th clock period. Most A/D converters latch the 8th bit of information in the SAR in the same manner as the first 7 bits, then on the 9th clock cycle the 8-bit result is available in a parallel format on the output pins of the SAR. The circuit shown in Figure 1 does not behave in the same manner. Rather than latching the LSB in the SAR at the end of the 8th clock cycle, the entire &bit result is latched into the parallel output registers at this time. This is accomplished by connecting the output of the SAR direction to the parallel register's inputs for the first 7 bits and connecting the 8th...