Browse Prior Art Database

LOCAL SYNCHRONOUS CLOCK GENERATORS FOR VLSI CIRCUITS

IP.com Disclosure Number: IPCOM000005437D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2001-Oct-10
Document File: 3 page(s) / 100K

Publishing Venue

Motorola

Related People

Ken Au: AUTHOR [+2]

Abstract

Local synchronous clock generators are implemented to provide synchronism in dynamic MOS cir- cuits between data paths which operate at various lower frequencies or with bursts from a higher fre- quency clock.

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LOCALSYNCHRONOUS CLOCK GENERATORS FOR VLSI CIRCUITS

By Ken Au and Jules Campbell

ABSTRACT

   Local synchronous clock generators are implemented to provide synchronism in dynamic MOS cir- cuits between data paths which operate at various lower frequencies or with bursts from a higher fre- quency clock.

INTRODUCTION

   In complex circuits such as speech synthesizers, dynamic MOS circuitry is utilized to reduce power and die area. However, data must be retained in registers and counters for long periods Of time relative to the main clock period. This requires a feedback path and a minimum clocking frequency to refresh data stored on node capacitances. Otherwise data could be lost or altered by leakage currents. Earlier design techniques used signal steering logic for each register bit, or a third clock phase, which was delayed from the slave clock phase, to drive a feedback coupler. However, the generation of mutually exclusive master clock phases can be used to sample new data or refresh old data onto the storage node.

DESCRIPTION

   Figure 1 is an example of the actual circuit environment where the clock signals are distributed throughout the integrated circuit. The main clock generator is free running at the highest internal fre- quency and provides the slave clock phase, OS, to all circuitry as well as a synchronizing clock, SK, to all local master clock generators. The slave clock phase should be generated in a manner which ensures non-overlap with the slowest transitions from any local master clock generator. This is accomplished by correct scaling of the master generators to their load capacitances and by the addition of an even number of delay stages in the slave clock generat...