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A HIGH SPEED POWER-DOWN DECODER CIRCUIT

IP.com Disclosure Number: IPCOM000005461D
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2001-Oct-10
Document File: 2 page(s) / 71K

Publishing Venue

Motorola

Related People

Clinton Kuo: AUTHOR

Abstract

The requirement of low power standby mode operation for today's static type MOS memories, such as ROM, EPROM and EEPROM, has degraded speed of these products due to a slower access time for chip enable than for an address, The slower chip enable access time is caused mainly by shortcomings of the existing power down decoder circuits that reset all word lines high and bit lines low during the power-down period. Discharging of all word lines, except the one selected, during power up creates a negative voltage on the bit lines through capacitive coupling. This can cause unselected column gating transistors to turn on which retards the transition of the selected bit line from low to high, resulting in longer chip enable access time.

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Technlcal Developments Volume 2 January 1982

A HIGH SPEED POWER-DOWN DECODER CIRCUIT By Clinton Kuo

DESCRIPTION Oi PROBLEM

   The requirement of low power standby mode operation for today's static type MOS memories, such as ROM, EPROM and EEPROM, has degraded speed of these products due to a slower access time for chip enable than for an address, The slower chip enable access time is caused mainly by shortcomings of the existing power down decoder circuits that reset all word lines high and bit lines low during the power-down period. Discharging of all word lines, except the one selected, during power up creates a negative voltage on the bit lines through capacitive coupling. This can cause unselected column gating transistors to turn on which retards the transition of the selected bit line from low to high, resulting in longer chip enable access time.

SOLUTION

   The,solution is a decoding scheme that resets all word lines low and all bit lines high during the power.down period. A row decoder circuit which satisfies low level voltage requirements for word lines and which dissipates no power (no DC current path) during the standby period is shown in the Figure below. The key is controlling natural transistors Ql and Q2 by the chip enable signal. All address outputs to the decoding circuit are low during the power down period. VW is an erase voltage, the application of which is controlled by VW.

RESULTS

   The new decoder circuit was incorporated in the design of Motorola'...