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IMPROVED SAMPLE AND HOLD CONTROL CIRCUITRY

IP.com Disclosure Number: IPCOM000005479D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2001-Oct-08
Document File: 2 page(s) / 113K

Publishing Venue

Motorola

Related People

Michael H. Retzer: AUTHOR

Abstract

Analog to digital converter systems operating on rapidly changing input waveforms require very small control signal jitter in the sampler to not degrade measurement performance. In addition, for systems employing a sample and hold, fast acquisition and low pedestal error nonlinearity are desirable. It is difficult to simultaneously achieve this with conventional FET switching. The circuit presented here offers improved performance by using a bipolar Gilbert cell to charge the holding capacitor. This configuration can be switched rapidly for low aperture jitter, with inherently zero dif- ferential pedestal error. The large charging currents which allow fast acquisition can be turned off dur- ing hold mode for low power dissipation.

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(@I MOTOROLA Technical Developments Volume 3 March 1983

IMPROVED SAMPLE AND HOLD CONTROL CIRCUITRY

By Michael H. Retzer

   Analog to digital converter systems operating on rapidly changing input waveforms require very small control signal jitter in the sampler to not degrade measurement performance. In addition, for systems employing a sample and hold, fast acquisition and low pedestal error nonlinearity are desirable. It is difficult to simultaneously achieve this with conventional FET switching. The circuit presented here offers improved performance by using a bipolar Gilbert cell to charge the holding capacitor. This configuration can be switched rapidly for low aperture jitter, with inherently zero dif- ferential pedestal error. The large charging currents which allow fast acquisition can be turned off dur- ing hold mode for low power dissipation.

CIRCUIT DESCRIPTION

   Figure 1 shows the sample and hold implementation. The input is coupled to one gate of the FET differential pair, Ql. The gate of Q2 monitors the feedback voltage signal from the storage capacitor, CH. The 5 mA bias current for the differential stage is supplied by the 03 and Q4 constant current network.

   FET's Ql and Q2 form a differential cascade amplifier with transistors 05 and Q6. The bases of Q5 and Q6 are biased at a fixed voltage by the 04 network. The differential voltage error signal appears at the collectors of 05 and 06. The gain of the stage is set by the collector and source resistors. The cascade configuration improves the speed of the stage in the sample mode by decreasing the input Miller effect capacitance.

   More importantly, the base of control transistor, 016, is biased at the same voltage as the bases of Q5 and Q6. During hold mode, control line A is brought to TTL logic level 1. This brings the 6.W zener diode Dl out of conduction, and approximately 6 mA is injected at the emitter of Q16. Since this current is greater than the 5 mA differential pair bias current, control transistor Q16 will saturate. This insures that Ql and Q2 will be pinched off and that 05 and 06 will be cut off during hold. During hold, the col- lector voltages of both Q5 and Q6 go to the positive rail. During sample mode, control line A is brought to TTL logic level 0. This cuts off control transistor Q16 and the differential amplifier operates normally.

   Note that it would also be possible to turn off the differential pair during hold mode by cutting off the bias transistor, Q3. For power reduction this works fine. However, letting the source ends of Ql and Q2 float allows the input signal to parasitical...