Browse Prior Art Database

RESETTABLE CURRENT LIMIT LATCH

IP.com Disclosure Number: IPCOM000005483D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2001-Oct-08
Document File: 2 page(s) / 80K

Publishing Venue

Motorola

Related People

Michael M. Stamler: AUTHOR

Abstract

In many large systems that derive power from a central power supply, there is a need to maintain system Integrity in the event one module fails and attempts to draw excessive current. A typical solu- tion is to use a dedicated fuse in series with each module that physically isolates it from the power sup- ply when its rating is exceeded. There are, however, instances where such an approach is impractical because of the high incidence of transient surges that exist.

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;j& MOTOR OLA Technlcal Developments Volume 3 March 1983 ,._.

RESETTABLE CURRENT LIMIT LATCH

By Michael M. Stamler

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  In many large systems that derive power from a central power supply, there is a need to maintain system Integrity in the event one module fails and attempts to draw excessive current. A typical solu- tion is to use a dedicated fuse in series with each module that physically isolates it from the power sup- ply when its rating is exceeded. There are, however, instances where such an approach is impractical because of the high incidence of transient surges that exist.

Such a situation exists in base station controllers using long telephone lines as the interface

e means which, by their nature, are susceptable to lightning strikes. These strikes cause momentary cur- rent surges which can either degrade or open a fuse. One consequence of this is the need to service the module when an unusual surge exists rendering the unit inoperable until fixed.

   To overcome this problem, a solid state resettable fuse was designed. It consists of a current sens- ing circuit Q3 and R6, a latch Q1 and Q2, a delay circuit R5 and Cl and a series pass switch Q4 and Q5. The switch is controlled by Q6 and Q7 which is enabled and disabled by an external signal. The external signal comes from a microprocessor l/O port.

   In normal operation, with a logic high at the input, the latch is held in a reset state via CR1 and the switch is off providing no current to the load. When a logic low is asserted, Q6 turns 05 and Q4 on pro- viding current to the...