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PROGRAMMABLE MEMORY ADDRESS DECODING FOR MICROPROCESSOR MEMORY DEVICES

IP.com Disclosure Number: IPCOM000005486D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2001-Oct-09
Document File: 2 page(s) / 99K

Publishing Venue

Motorola

Related People

David Paldan: AUTHOR

Abstract

The widespread use of a-bit microprocessor based controllers has resulted in a large and varied of- fering of E-bit memory devices for use with them. In the E-bit format memory manufacturers offer e ROMs, EPROMs, EEPROMs, static RAMS and others. Furthermore, these devices are available in 1 Kx8, 2Kx8, 4Kx8 and a variety of other sizes. While there is a JEDEC pinout standard that can be used in a memory circuit layout, devices of nominally the same type and size may require incompatible timing relationships between control signals. Once the memory designer has selected a device, it is difficult to change the layout to replace a memory device with one that becomes cheaper, larger or more widely supported.

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Volume 3 March 1983

PROGRAMMABLE MEMORY ADDRESS DECODING FOR

MICROPROCESSOR MEMORY DEVICES

By David Paldan

The widespread use of a-bit microprocessor based controllers has resulted in a large and varied of- fering of E-bit memory devices for use with them. In the E-bit format memory manufacturers offer

e ROMs, EPROMs, EEPROMs, static RAMS and others. Furthermore, these devices are available in 1 Kx8,

2Kx8, 4Kx8 and a variety of other sizes. While there is a JEDEC pinout standard that can be used in a memory circuit layout, devices of nominally the same type and size may require incompatible timing

relationships between control signals. Once the memory designer has selected a device, it is difficult

.\ to change the layout to replace a memory device with one that becomes cheaper, larger or more widely supported.

   To make the memory design more flexible, it is possible to replace the chip select decoding net- work typically made of AND-OR gates with one made from a programmable logic array(or other PROM). The number of signals that must be controlled by this device remains manageable due to the common pin selection for most address and data lines. The few remaining unique signals (chip enable, output enable, read/write, etc.) must be provided by the logic array to the specific memory device as required.

   For example, a memory design using two 2Kx8 EPROMs (2716) and two 2Kx6 RAMS (6116) could be reconfigured to a design using two 4Kx8 EPROMs (2732) and two 2Kx8 RAMS keeping a common 24 pin layout (see figure 1). Addresses A0 thru A9 and data lines DO thru D7 for these devices are located in the same relative position and are connected directly to the address and data bus. The remaining signals are provided by the programmable logic array. These are multiplexed to the memory IC's to simplify logic array requirements.

   The logic array generates a chip select bus (CSO,CSl) to ide...