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A HIGH SPEED, LOW NOISE, SYNCHRONIZER CIRCUIT WITH A SQUARE WAVE OUTPUT

IP.com Disclosure Number: IPCOM000005490D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2001-Oct-09
Document File: 3 page(s) / 104K

Publishing Venue

Motorola

Related People

Kenneth A. Hansen: AUTHOR

Abstract

Logic designs are typically done asynchronously because the design is simplified, the number of gates is minimized, and the current drain is minimized. However, in an a synchronous design it is often required to synchronize with respect to some reference time base. Various approaches have been used in the past to perform the synchronization. The simplest approach uses a D type flip-flop as asyn- chronizer. All of these approaches have at least one of the following shortcomings: (1) slow speed, (2) 'i high noise, or (3) non-square wave output.

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MOTOROLA Technlcal Developments Volume 3 March 1983

A HIGH SPEED, LOW NOISE, SYNCHRONIZER CIRCUIT WITH A SQUARE WAVE OUTPUT

By Kenneth A. Hansen

   Logic designs are typically done asynchronously because the design is simplified, the number of gates is minimized, and the current drain is minimized. However, in an a synchronous design it is often required to synchronize with respect to some reference time base. Various approaches have been used in the past to perform the synchronization. The simplest approach uses a D type flip-flop as asyn- chronizer. All of these approaches have at least one of the following shortcomings: (1) slow speed, (2)

'i high noise, or (3) non-square wave output.

   A high performance synthesizer utilizing a sample and hold phase detector requires a square wave reference divider signal. In addition, for use in a high performance low noise communications channel, the jitter noise output of this signal must be minimized. This particular circuit application required a high speed, low noise, synchronizer circuit with a square wave output. An implementation of the circuit that is easily integratable is shown in Figure 1. Although it is shown as PL (single input, multiple out- puts), it could also be implemented in any of the more conventional multiple input, single output logic families.

   The circuit in Figure 1 is used to provide a synchronous output from a cascaded set of asyn- chronous counters (gates 1-6 and blocks A-Z). The synchronizer consists of gates 30-42. The syn- chronizer gates function as follows:

gates 30,33: guarantee edge triggered operation gates 31,32,36,37
gates 38-42:

S-R latch that passes synchrontzed data to fR output S-R latch used as shift register to feedback control data to input of synchronizing output
gates 52,51: are functionally duplicates of gates 5 and 6, respectively
fR: synchronized output...