Browse Prior Art Database

PAL IMPLEMENTED STATE MACHINE FOR MC6818

IP.com Disclosure Number: IPCOM000005509D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2001-Oct-10
Document File: 1 page(s) / 51K

Publishing Venue

Motorola

Related People

Charles Kirtland: AUTHOR

Abstract

The control interface for the MC6818 real time clock can be a problem for printed circuit boards where real estate is at a premium. An alternative to a Johnson counter and gates is to build a state machine inside a PAL. The PAL is an AND-OR network with certain devices also containing D flip flops. This architecture allows several packages to be realized inside one package while retaining maximum flexibility of clock speeds.

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fm MOTOROLA Technlcal Developments

Volume 3 March 1983

PAL IMPLEMENTED STATE MACHINE FOR MC6618

By Charles Kirtland

   The control interface for the MC6818 real time clock can be a problem for printed circuit boards where real estate is at a premium. An alternative to a Johnson counter and gates is to build a state machine inside a PAL. The PAL is an AND-OR network with certain devices also containing D flip flops. This architecture allows several packages to be realized inside one package while retaining maximum flexibility of clock speeds.

   The complete interface shown here was designed for MC88000 or VERSAbus interface at any clock speed from 8MHz to 16 MHz. It also improves reliability by reducing the required chip count and inter- connections between devices.

   The STATE COUNTER inside the PAL need only count in straight binary with appropriate AND terms of Data Strobe and Real Time Clock Select (RTCSEL) to initialize the sequence and maintain the count system setup. The STROBE CONTROL uses the state counter to keep track of the time required for each control output. These control outputs generate the signals required by the Address-Data Multiplexer and the strobes for the RTC. It also generates DTACK for the system Data Acknowledge.

   The PAL interface wait states the bus until the minimum cycle time for the RTC has passed if two consecutive cycles to the RTC are executed (since the system can probably respond quicker than the RTC).

The PAL can realize almost the e...