Browse Prior Art Database

Methods of Scan Pattern Manipulation

IP.com Disclosure Number: IPCOM000005542D
Original Publication Date: 2001-Oct-12
Included in the Prior Art Database: 2001-Oct-12
Document File: 5 page(s) / 597K

Publishing Venue

Motorola

Related People

John C. Potter: AUTHOR [+2]

Abstract

In the world of System-on-a-Chip (SoC) integration, one of the more significant cost drivers is the test integration. The volume of logic and memory, coupled with the volume of vectors and separate vector sets, requires test scheduling to meet power, package, test bandwidth, and tester limitations. Test scheduling has two main components, a test architecture that allows or enables test selectable portions of the chip, and techniques for combining test groupings into schedulable sections. This publication discusses several methods of scan pattern and BIST pattern manipulation for scheduling, the test architecture requirements, and the information needed to perform the test pattern manipulation.

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Methods of Scan Pattern Manipulation

John C. Potter and Alfred L. Crouch

Abstract

In the world of System-on-a-Chip (SoC) integration, one of the more significant cost drivers is the test integration. The volume of logic and memory, coupled with the volume of vectors and separate vector sets, requires “test scheduling” to meet power, package, test bandwidth, and tester limitations. Test scheduling has two main components, a test architecture that allows or enables test selectable portions of the chip, and techniques for combining test groupings into schedulable sections. This publication discusses several methods of scan pattern and BIST pattern manipulation for scheduling, the test architecture requirements, and the information needed to perform the test pattern manipulation.

Virtual Component Signature

Virtual components (VC) have a unique information signature that fully describes them. Part of this unique signature is the “test signature” which includes all items needed to integrate or manipulate a core or its vector set. Test signature items may include:

§         the core name or unique designation;

§         test capability (Scan, BIST, Memory BIST – list);

§         scan chain bus width (maximum, and as delivered);

§         as delivered scan chain bit depth (a.k.a. shift depth);

§         scan chain configuration options (as width and depth);

§         BIST or other test signals;

§         test setup sequence;

§         number of test vector files;

§         pattern depth;

§         power consumption (peak, average, di/dt – per pattern file);

§         vector data rate (e.g., the shift data frequency);

§         vector sample rate (e.g., the sample clock frequency);

§         whether the core supports a test access mechanism (e.g., scan wrapper);

§         whether a quiescent or safety state is supported;

§         fault models supported;

§         fault coverage per test type (BIST, Scan, etc.) and per fault class (stuck-at, transition, toggle, etc.);

Figure 1 depicts two embedded cores with different signatures.  Core A has 32 scan chains, 300 bits of shift depth, 2000 scan patterns, and uses a quarter watt of power; whereas Core B has 16 scan chains, 152 bits of shift depth, 1000 scan patterns, and uses an eighth watt of power.  For purposes of discussion, the scan patterns represent stuck-at patterns.

However, as part of the VCs signature, other structural pattern types are included in the VC signature such as those that target transition delay, path delay, and Iddq (current leakage) faults.  In addition, there may be functional or behavioral patterns.

Figure 1:  VC Signature

The Problem

The goal is to take the representation of the core test signature above, and to use that information to somehow “efficiently” schedule tests. The key is to select the order in which vector sets are applied, and which vector sets that are to be applied simultaneously. This can be driven from the test architecture (combining scan chains end-to-end forces the patterns to be applied simultaneously and one core after the other), or it can be driven by the vectors (determining which...