Browse Prior Art Database

IMPROVED PROCESS FOR SELF-ALIGNED SCHOTTKY MOSFET

IP.com Disclosure Number: IPCOM000005571D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2001-Oct-16
Document File: 2 page(s) / 77K

Publishing Venue

Motorola

Related People

Tony Alvarez: AUTHOR

Abstract

It is highly desirable in the integrated circuit art to produce MOSFETs in which the source and drain contacts are self-aligned to the gate contact and whose positioning with respect to the gate contact is precisely controlled. The following describes an improved process for producing self-aligned MOSFETs in which the source drain regions are provided by silicide Schottky barriers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

MOTOROLA Technical Developments Volume 5 October 1985

IMPROVED PROCESS FOR SELF-ALIGNED SCHOTTKY MOSFET

by Tony Alvarez

   It is highly desirable in the integrated circuit art to produce MOSFETs in which the source and drain contacts are self-aligned to the gate contact and whose positioning with respect to the gate contact is precisely controlled. The following describes an improved process for producing self-aligned MOSFETs in which the source drain regions are provided by silicide Schottky barriers.

   Fig. 1 shows a portion of silicon substrate 10 covered by oxide layer 11 on which has been placed poly-silicon region 12. This structure is then exposed (Fig. 2) to implant ions 13 (typically Boron) to produced doped areas 14 in substrate 10. Doped areas 14 will extend very slightly under the edges of gate 12 due to the redistribution of impurities 13 during implant anneal.

   Oxide 15 is then uniformly deposited over the surface of this structure (Fig. 3). Anisotropic etching, as for ex- ample reactive ion etching as indicated by arrows 18, which is particularly selective to etch oxides is then used to remove portions 15a and 15b of oxide layer 15 leaving behind portions 15~ of oxide layer 15 (Fig. 4). An addi- tional reactive ion etch, as illustrated by arrows 19 but particularly selective to etch silicon substrate 10, is now provided to remove portions 14a of doped region 14 leaving behind portions 14b of doped region 14 which are protected by regions 15c of oxide lay...