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INITIALIZATING MICRO-COMPUTER PERIPHERALS

IP.com Disclosure Number: IPCOM000005581D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2001-Oct-17
Document File: 3 page(s) / 110K

Publishing Venue

Motorola

Related People

Brian Wilkie: AUTHOR

Abstract

The normal technique of initialisating peripheral circuits attached to a microprocessor bus by means of writing to internal registers is not sufficient for some situations. The MC66HC25, a peripheral designed to replace 2 ports on several different microcomputers operating in expanded mode, is a case in point. Since it also provides chip select signals to the memories in minimum chip count systems the part has to know in advance of the reset signal being disasserted the memory map required both for its own internal registers and that of the memories it is con- trolling.

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m MOTOROLA Technical Developments October 1985

INITIALIZATING MICRO-COMPUTER PERIPHERALS

   The normal technique of initialisating peripheral circuits attached to a microprocessor bus by means of writing to internal registers is not sufficient for some situations. The MC66HC25, a peripheral designed to replace 2 ports on several different microcomputers operating in expanded mode, is a case in point. Since it also provides chip select signals to the memories in minimum chip count systems the part has to know in advance of the reset signal being disasserted the memory map required both for its own internal registers and that of the memories it is con- trolling.

   The MC66HC25 utilizes 8 bits of mode select information. Pin count considerations clearly prevent the use of 6 dedicated mode select pins. One technique considered was to use the same method as the mode selection for the M6801 family of single chip microcomputers. This uses I/O port pins as mode inputs before the reset signal rises to signify the ending of the reset condition. Using special level sensing circuits allows resistors tied to Vcc to specify a mode select high signal while mode select low is defined by tying the pin to reset via a silicon diode. This works adequately but requires care in designing any circuitry connected to the I/O pin in normal operation.

   As can be seen from the block diagram (Fig. 1) the 66HC25 provides 2 more functions which allow a more innovative approach to solving the initialization problem. The reset for the system is input to the 68HC25 which in turn supplies the reset output to the CPU. This ensures an orderly reset sequence without any problems of one circuit recognizing reset earlier than another as can occur with a slow ramp on reset provided by an R/C time constant. The other function is to demultiplex the lower order address lines which are output during the Address Strobe (AS) high time on the 6601 style bus. This lower order address is then output for use by the external memories.

   The mode select information can be stored in the external memory...