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LEVEL SHIFTING NETWORK FOR REDUCING POWER IN BATTERY OPERATED INTEGRATED CIRCUITS

IP.com Disclosure Number: IPCOM000005583D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2001-Oct-17
Document File: 1 page(s) / 46K

Publishing Venue

Motorola

Related People

John Mahabadi: AUTHOR

Abstract

A level shifting network is provided that will considerably reduce the dynamic current at a given frequency for battery operated integrated circuits. This results in extended battery life and cost savings.

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MOTOROLA Technical Developments Volume 5 October 1985

LEVEL SHIFTING NETWORK FOR REDUCING POWER IN BATTERY OPERATED INTEGRATED CIRCUITS

by John Mahabadi

A level shifting network is provided that will considerably reduce the dynamic current at a given frequency for battery operated integrated circuits. This results in extended battery life and cost savings.

   The level shifting circuit for driving a load at Vour is shown in the single figure. An input signal V,, is provided to the gates of inverter transistors P, and N,, and to transmission gate P,/N,. Transmission gate PJN, is in an "ON" condition as long as power is applied. The outputs of inverter P,/N, and transmission gate PJN, are ap- plied to the gates of transistors N, and N,, respectively. Cross coupled network P,/N, and P,/N, provide the level shifting from V,, to V,,. lnverter PdN, is used as a buffer for driving the load.

   In the absense of transmission gate P,/N,, the input signal at the gate of transistor N, is delayed by the amount of inverter P,/N, delay. This delay is substantially long due to low operation voltage. During this delay, both transistors N, and N, are "ON". Since N, was "ON" at initial conditions, P, will be "ON" during the delay causing current to flow from V,, to ground through transistors P, and N,.

The addition of transmission gate PJN, balances the complementary signals at the gates of transistors N, and N, causing minimum current flow from V,, to ground.

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