Browse Prior Art Database

A TESTABLE STANDARD CELL FAMILY

IP.com Disclosure Number: IPCOM000005584D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2001-Oct-17
Document File: 5 page(s) / 168K

Publishing Venue

Motorola

Related People

Mark David Warlick: AUTHOR

Abstract

The growth in the application specific integrated circuit (ASIC) marketplace is predicted to be at a compound growth rate of over 33% for the next five years. This represents a growth in the number of integrated circuits defined each year from a few hundred to several thousand. Each of these new circuits requires a test program to assure the manufactured part meets the design specifications. EDN estimated in its report, The Semicustom ICRevolutiont, that by 1991 75% of all test programs will be written by IC customers and 50% of all manufacturing costs will be test costs.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 46% of the total text.

Page 1 of 5

m MO7OROLA Technical Developments

October 1985

A TESTABLE STANDARD CELL FAMILY

by Mark David Warlick

presented by Robert C. Turner

   The growth in the application specific integrated circuit (ASIC) marketplace is predicted to be at a compound growth rate of over 33% for the next five years. This represents a growth in the number of integrated circuits defined each year from a few hundred to several thousand. Each of these new circuits requires a test program to assure the manufactured part meets the design specifications. EDN estimated in its report, The Semicustom ICRevolutiont, that by 1991 75% of all test programs will be written by IC customers and 50% of all manufacturing costs will be test costs.

   The problem for a semiconductor manufacturer is to create an ASIC family of parts that are testable within the following constraints: fewest number of additional design guidelines; the smallest area penalty; the smallest performance penalty; is independent of the logic implemented; easily fits into most customers' design method- ology; is readily learned; is easily implemented in the CAD and Test support systems; and does not require ex- cessive tester time.

   The technique proposed here is a modified divide and conquer approach. Figure 1 illustrates a typical stan- dard cell circuit. It was designed hierarchically and has a complexity of several hundred gates. It consists of several subsystems and then standard cells within those subsystems. The test program will be difficult and expensive to create. The manufacturer has no knowledge of the internal logic or the chip function complicating the test program generation problem. However, if a technique can be developed that reduces the complexity of the circuit, then the testing problems can be reduced.

   Figure 2 shows the same circuit in a test mode. Most of the components in the circuit are reduced to "pass thru" logic. The test circuitry selects and isolates the subsystems for testing. By reducing the complexity, the amount of time required to test that section is substantially reduced.

   Accomplishing this requires the semiconductor manufacturer to build each standard cell element such that an input can change each cell's mode from its normal function to a simple buffer or inverter. Figures 3, 4 and 5 show three elements of a standard cell library, a 3 input NAND gate, a 3 input NOR gate, and a D type flip/flop. Figures 3 and 4 show the logical element, a NAND or NOR when the control line is zero. When the control line is one, the NAND and the NOR gate become inverters. The schematics in Figures 3 and 4 are depletion mode NMOS and represent a possible implementation of this test strategy. The NAND gate from Figure 3 can be used to develop the D Flip/Flop in Figure 5. With the control line equal to zero, the part is a standard flip/flop. When the control line is one, the six three input NAND gates become inverters. The D Flip/Flop can then be modeled as a series of four inverters.

   The test...