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A HIGH SPEED OUTPUT BUFFER

IP.com Disclosure Number: IPCOM000005586D
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2001-Oct-17
Document File: 2 page(s) / 100K

Publishing Venue

Motorola

Related People

Mark Bluhm: AUTHOR

Abstract

Figure 1 illustrates a high speed output buffer circuit where in the data is stored only one delay stage from the gate electrodes of output driver devices 1 and 2.

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MOTOROLA Technical Developments Volume 5 October 1985

A HIGH SPEED OUTPUT BUFFER

by Mark Bluhm

Figure 1 illustrates a high speed output buffer circuit where in the data is stored only one delay stage from the gate electrodes of output driver devices 1 and 2.

   The data appearing at terminal 3 (DATA) is applied to a first input of NAND gate 4, the output of which is ap- plied to a first input of NAND gate 5 and to the gate electrodes of P-channel field effect transistor 8 and N-channel field effect transistor 7, respectively. The tristate control signal (TRISTATE) is applied via input terminal 8 to first inputs of NOR gates 9 and 10 respectively and to the input of inverter 11, the output of which is coupled to second inputs respectively of NAND gates 4 and 5.

The output NAND gate 5 is coupled to the gate electrodes of P-channel field effect transistor 12 and N-channel field effect transistor 13 respectively. The source electrodes of transistors 12 and 13 are coupled respectively to a source of supply voltage Vdd and to ground. The drain electrode of transistors 12 and 13 are coupled to the source electrodes of P-channel field effect transistor 14 and N-channel field effect transistor 15. The drain elec- trodes of transistors 14 and 15 are coupled to the gate electrode of output driver transistor 1 and inverter 18. The output of inverter 18 is coupled to the second input of NOR gate 9.

The source electrodes of transistors 8 and 7 are coupled respectively to a source of supply voltage Vdd and to ground. The drain electrodes are coupled respectively to the source electrodes of P-channel field effect transistor 17 and N-channel field effect transistor 18. The drain electrodes of transistors 17 and 18 are coupled to the gate electrode of output driver transistor 2 and inverter 19. The output of inverter 19 is coupled to the second input of NOR gate 10. The output of NOR gates 9 and 10 are coupled respectively to the gate electrodes of output driver devices 1 and 2 via transmission gates 20 and 21 respectively. Transmission gates 20 and 21 are opened when clocksignal Cl is high and clock signal C2 is low, as for example during time T2 in FIG. 2.

   Assuming that the TRISTATE signal appearing at terminal 8 is low, logical high signals will be applied to the second inputs of NAND gates 4 and 5, thus enabling each gate...