Browse Prior Art Database

Process For Forming A Semiconductor Device

IP.com Disclosure Number: IPCOM000005590D
Original Publication Date: 2001-Oct-17
Included in the Prior Art Database: 2001-Oct-17
Document File: 19 page(s) / 62K

Publishing Venue

Motorola

Related People

Sergio A. Ajuria: AUTHOR [+4]

Abstract

A process forms trench field isolation for a semiconductor device. After forming a planarization-stop layer over a substrate, an opening through the planarization-stop layer and a trench in the substrate are formed. In one embodiment, a trench fill material fills the trench without using a trench liner, In other embodiments, a trench liner is formed before filling the trench. The trench fill material is exposed to an H2O-containing ambient, wherein a portion of the substrate at the trench walls is oxidized during this step. A portion of the trench fill material that overlies the planarization-stop layer is then removed. The process is particularly useful in devices with a plurality of etches and cleans due to the use of different gate dielectric layer thickness, such as devices that include a nonvolatile memory array.

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PROCESS FOR FORMING A SEMICONDUCTOR DEVICE

Field of the Invention

                  This invention relates in general to processes for forming semiconductor devices, and more particularly, to processes for forming those devices with trench field isolation regions.

Background of the Invention

                  Semiconductor devices require smaller dimensions as performance requirements for those devices increase.  Conventional field isolation processes, such as local oxidation of silicon (LOCOS) and modified LOCOS processes are inadequate for the small dimensions required for future electronic devices.  Shallow trench isolation can form narrow field isolation regions that adequately isolate components within a semiconductor substrate from one another.  One conventional way of forming trench field isolation is to form a pad dielectric layer and silicon nitride layer over a semiconductor substrate.  After forming a trench within a substrate, a thermal oxide liner is then formed along the exposed edges of the trench.  The trench is then filled with a deposited trench fill material.  After planarization, the nitride and pad dielectric layers are removed. 

                  A problem with the previously described shallow trench isolation occurs when forming a semiconductor device that has a plurality of oxide etches and cleans.  These oxide etches and cleans are particularly problematic for semiconductor devices having more than one gate dielectric layer.  An example of this could include a semiconductor device, such as a microcontroller or microprocessor that has a logic portion and a nonvolatile memory array.  Typically, the memory cells (within a memory array) include a first gate dielectric layer, usually referred to as a tunnel dielectric layer, while the logic areas (outside the memory array) include a high-voltage area with a thicker gate dielectric layer and a low-voltage area with a thinner gate dielectric layer (relative to the gate dielectric layer used for the high-voltage area). 

                  During the formation of the device, repeated etch backs cause the trench fill material, particularly along the edges of the trench, to be etched away at an accelerated rate.  Referring to FIG. 1, a liner layer as 12 and a trench fill material 14 lie within a portion of a semiconductor substrate 10.  The etched regions 16 have been formed by the a plurality of etches and cleans necessary to form the different gate dielectric layers.  As can be seen in FIG. 1, the corners 18 of the substrate near the top of the trench are sharp. 

                  As shown in FIG. 2, when a second or subsequent gate dielectric layer 19 is formed, the thickness of the gate dielectric layer 19 at the corner 18 can be significantly thinner compared to other portions.  A gate electrode (not shown) is formed over the gate dielectric layer 19 and trench fill material 14.  The gate dielectric layer 19 is locally thinner at the corner 18 and can cause premature gate dielectric breakdown between the substrate 10 and the gate electrode. 

                  One attempt to reduce the effects is to...