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SEPARATION OF EXCEPTION RECOGNITION, PRIORITIZATION, AND STATE MAINTENANCE

IP.com Disclosure Number: IPCOM000005599D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-18
Document File: 1 page(s) / 81K

Publishing Venue

Motorola

Related People

Bill Moyer: AUTHOR [+3]

Abstract

As processors become increasingly complex, so do the exception recognition and handling requirements of the processor. Complex processors, such as the MC68000, MC68010, and MC68020 were designed to recognize and handle a number of internally and externally generated exception conditions. Among these are interrupts, bus errors, addressing errors, illegal instruction, privilege violations, division by zero, trace exceptions, emula- tion exceptions, and other various exceptions which might occur in a processing system.

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MOTOROLA Technical Developments Volume 6 October 1986

SEPARATION OF EXCEPTION RECOGNITION, PRIORITIZATION, AND STATE MAINTENANCE

by Bill Moyer, Doug MacGregor and Bob Thompson

   As processors become increasingly complex, so do the exception recognition and handling requirements of the processor. Complex processors, such as the MC68000, MC68010, and MC68020 were designed to recognize and handle a number of internally and externally generated exception conditions. Among these are interrupts, bus errors, addressing errors, illegal instruction, privilege violations, division by zero, trace exceptions, emula- tion exceptions, and other various exceptions which might occur in a processing system.

   The MC68000and MC68010 had an integrated exception recognition and exception processing mechanism. Exceptions were detected, prioritized, and latched by specialized internal hardware consisting of a priority PLA, and an exception latch whose contents were used to form an exception vector This exception vector points to an area in main memory where the entry point address for an exception handler can be found. Upon excep- tion recognition, the processor stacks a varying amount of internal state information along with a stack format number, and then reloads its program counter with the value obtained from the exception vector location, and begins instruction execution for the exception handler. The value stored in the exception latch is also used to indicate the current exception state. This state information may be used to modify the normal operation of the processor if another exception is detected. An example of this is the "double bus fault" exception which can occur during the handling of a bus error or an addressing error exception. In this case, another bus error exception does not re-initiate bus error exception processing. Instead, it indicates a non-recoverable error con- dition, and the processor shuts itself down to avoid system corruption.

   In a more complex processor, such as the MC68020, it i...